Purpose: The purpose of this paper is to study the Manufacturers pallet-loading problem (MPLP), by loading identical small boxes onto a rectangle pallet maximise utilization percentage while reducing Complexity loading.Design/methodology/approach: In research Block approach proposed using Mixed integer linear programming (MILP) model that generates layouts an improved structure, which very effe...

Hsin-I Liu Vito Dai Avideh Zakhor Borivoje Nikolić University of California, Berkeley Department of Electrical Engineering and Computer Science Berkeley, California E-mail: [email protected] Abstract. Achieving the throughput of one wafer layer per minute with a direct-write maskless lithography system, using 22-nm pixels for 45-nm feature sizes, requires data rates of about 12 Tb/s. In ou...

The paper deals with a suitably designed system that is being used to separate textual regions from graphics regions and locate textual data from textured background. We presented a method based on edge detection to automatically locate text in some noise infected grayscale newspaper images with microfilm format. The algorithm first finds the appropriate edges of textual region using Canny edge...

A document image is a visual representation of a paper document, such as a journal article page, a cover page of facsimile transmission, ooce correspondence, an application form, etc. Document image understanding as a research endeavor consists of developing processes for taking a document through various representations: from scanned image to semantic representation. This paper describes docum...

Most existing appearance models for visual tracking usually construct a pixel-based representation of object appearance so that they are incapable of fully capturing both global and local spatial layout information of object appearance. In order to address this problem, we propose a novel spatial LogEuclidean appearance model (referred as SLAM) under the recently introduced Log-Euclidean Rieman...

From the in-beam tests of the PADI1 prototype [1] we have recognized that the minimization of the crosstalk between channels has a priority for further developments. In the upcoming design we have changed the biasing type from voltage biasing to current biasing. The bias block used in PADI2-3 ASIC is a constant-transconductance bias circuit having a wide swing cascode current mirrors similar to...

The promise of future many-core processors, with hundreds of threads running concurrently, has lead the developers of linear algebra libraries to rethink their design in order to extract more parallelism, further exploit data locality, attain a better load balance, and pay careful attention to the critical path of computation. In this paper we describe how existing serial libraries like (C-)LAP...

Abstract As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are the most effective and popular techniques to reduce interconnect delay and are traditionally applied to post-layout optimization. As the SIA technology roadmap predicts, however, the number of interconnections...

We address the problems of I/O scheduling and buffer management for general reference strings in a parallel I/O system. Using the standard parallel disk model withD disks and a shared I/O buffer of size M , we study the performance of on-line algorithms that use bounded global M block lookahead. We introduce the concept of write-back whereby blocks are dynamically relocated between disks during...

Robust phenotypic data allow adequate statistical analysis and are crucial for any breeding purpose. Such data is obtained from experiments laid out to best control local variation. Additionally, experiments frequently involve two phases, each contributing environmental sources of variation. For example, in a former experiment we conducted to evaluate production related traits in Pelargonium zo...