This paper presents the INSIDE system that rapidly searches the design space for extensible processors, given area and performance constraints of an embedded application, while minimizing the design turn-around-time. Our system consists Of a ) a methodology to determine which code segments are most suited for implementation a5 a set of extensible instructions, b) a heuristic algorithm to select...

Processing in memory (PIM) implemented via 3D die stacking has been recently proposed to reduce the widening gap between processor and memory performance. By moving computation that demands high memory bandwidth to the base logic die of a 3D memory stack, PIM promises significant improvements in energy efficiency. However, the vision of PIM implemented via 3D die stacking could potentially be d...

A review paper on the various VLSI architectures of fuzzy logic based processors and controllers is presented over here. The focus of this paper on the study of low power VLSI implementation of fuzzy processors to result in reduced silicon area, high operating speed and the adaptability to various application domains. The paper reviews the design and implementation of different components of a ...

Given a set of operations specified by their execution time intervals {[ai,zi)|i=1, ..., n}, where ai<zi, a processor-optimal allocation (POA) problem is to allocate the minimum number of processors to execute these operations, where any two operations [aj,zj) and [ak,zk) executed by a processor have the property of either zj≤ak or zk≤aj. A weighted version of the POA problem is to find a proce...

Streaming processing of XML transformations is practically needed especially when large XML documents or XML data streams are to be transformed. In this paper, the design of an automatic streaming processor for XSLT transformations is presented. Unlike other similar systems, our processor guarantees bounds on the resource usage for the processing of a particular type of transformation. This fea...

An integrated microfluidic processor is developed that performs molecular computations using single nucleotide polymorphisms (SNPs) as binary bits. A complete population of fluorescein-labeled DNA "answers" is synthesized containing three distinct polymorphic bases; the identity of each base (A or T) is used to encode the value of a binary bit (TRUE or FALSE). Computation and readout occur by h...

A novel configurable processor architecture is presented for detecting Spatially Multiplexed (SM) data in a high order (4x4) multiple-input-multiple-output (MIMO) wireless systems. It is a customized architecture to match an algorithm that provides “soft” values to the Forward Error Decoder (FEC), with systolic-like data and control flow. The processor is able to switch between three different ...

FPGA implementation of 64-bit execute unit for VLIW processor, and improve power representation have been done in this paper. VHDL is used to modelled this architecture. VLIW stands for Very Long Instruction Word. This Processor Architecture is based on parallel processing in which more than one instruction is executed in parallel. This architecture is used to increase the instruction throughpu...

Novel very large-scale integration architectures and a design methodology for adder-based residue number system (RNS) processors are presented in this paper. The new architectures compute residues for more than one modulus either serially or in parallel, while their use can increase the resource utilization in a processor. Complexity is reduced by sharing common intermediate results among the v...