This paper reports on the implementation of an Artificial Neural Network (ANN) on an Atmel AT6005 Field Programmable Gate Array (FPGA). The work was carried out as an experiment in mapping a bit-level, logically intensive application onto the specific logic resources of a fine-grained FPGA. By exploiting the reconfiguration capabilities of the Atmel FPGA, individual layers of the network are ti...

"Cadence provides the FPGA-based Protium platform with emulation-like are certainly supportable, with the manual optimizations described above. Yet, the Frank offered some details on the Protium “FPGA-based emulation” methodology. In respect to methodology you of course can refer to the FPGA-based Prototyping Methodology Manual, FPMM. (English and Japanese versions, 英語版と日本語. This survey data is...

Networked reconfiguration is an enabling technology for cost effective service deployment and maintenance. A hardware virtual machine to enable this networked reconfiguration is presented. An abstract FPGA model is the core of such a hardware virtual machine. Based on this abstract FPGA model, the traditional implementation flow of FPGA has been separated into two parts: the service provider’s ...

The development of digital IIR (Infinite Impulse Response) filter is done on VIRTEX-6 FPGA using VHDL (Very High Speed Integrated Circuit Hardware Description Language) in XILINX Integrated Software Environment. IIR filter is analytically simulated by simulink environment in MATLAB. The digital data output of A/D converter is sent through IIR module in FPGA. Testing and debugging IIR module is ...

The scientific community has been using FPGA-based computation engines as cellular automata (CA) accelerators for some time now. With the recent advent of more advanced FPGA logic it becomes necessary to better understand the mapping of CA to these systems. In this paper, we present a methodology to predict the performance of running such CA on specific FPGA hardware before engineering the desi...

This paper presents an asynchronous FPGA that combines 4-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. 4-phase dual-rail encoding is employed to achieve small area and low power for function units, while LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters...

As a good trade-off between CPU and ASIC, FPGA is becoming more widely used in both industry and academia. The increasing complexity and scale of modern FPGA, however, impose great challenges on the FPGA placement and packing problem. In this paper, we propose RippleFPGA to solve the packing and placement simultaneously through a set of novel techniques, such as (i) smooth stair-step flow, (ii)...

Future generation embedded multicore will be based on hundreds of processors connected through Network on Chip (NOC) . Design productivity of embedded multicore is a major challenge for the semiconductor industry. In this paper, an automatic very large scale NoC design methodology based on FPGA IP is proposed to accelerate the embedded multicore design productivity using very large scale multi-...