3D-NAND flash memory provides high capacity per unit area by stacking 2D-NAND cells having a planar structure. However, because of the nature lamination process, frequency error occurrence varies depending on each layer or physical cell location. This phenomenon becomes more pronounced as number write/erase (Program/Erasure) operations increases. Error correction code (ECC) is used for in major...

Semiconductor technology scaling makes NAND flash memory subject to continuous raw storage reliability degradation, leading to the demand for more and more powerful error correction codes. This inevitable trend makes conventional BCH code increasingly inadequate, and iterative coding solutions such as low-density parity-check (LDPC) codes become very natural alternative options. However, fine-g...

Error correction in high density multilevel cell NAND flash memories is of great concern and Low-DensityParity-Check (LDPC) codes are attracting much interest due to their Shannon-capacity-approaching behavior. In this work, the error performance of very large block length quasi-cyclic (QC) LDPC codes is evaluated through a high speed FPGA based emulator. A novel algebraic QC-LDPC code of rate ...

This paper presents a set of models dedicated to describe a flash storage subsystem structure, functions, performance and power consumption behaviors. These models cover a large range of today's NAND flash memory applications. They are designed to be implemented in simulation tools allowing to estimate and compare performance and power consumption of I/O requests on flash memory based storage s...

The threshold voltage distribution after ideal programming in NAND flash memory cells is usually distorted by a combination of the random telegraph noise (RTN), cell-to-cell Interference (CCI), and the retention process. To decide the original bits more accurately in this scenario, a precise channel model shall be utilized on the basis of the measured threshold voltages. This paper aims to char...

The reliability issues of Flash electrically erasable programmable read-only memory (Flash EEPROM) are reviewed in this paper. The reduction of the memory cell size and improvement in the reliability have been realized by several breakthroughs in the device technology; in particular, the reliability of the ETOX and NAND structure EEPROM will be discussed in detail. Flash EEPROM is expected to b...

This paper describes the formal modeling and analysis of a design for a flash-based filesystem in Alloy. We model the basic operations of a filesystem as well as features that are crucial to NAND flash hardware, such as wear-leveling and erase-unit reclamation. In addition, we address the issue of fault tolerance by modeling a mechanism for recovery from interrupted filesystem operations due to...

Today Nand Flash memory is not only used in hand hold electronic devices but also as secondary storage medium. It serves as an alternative to Hard Disk Drives (HDDs) in the form of Solid State Dives (SDDs). However, unlike HDD flash memory does not support in place update, i. e. for updating data, old data can not be replaced by new data. Data can be written only at clean i. e. already erased p...

This paper presents dynamic sector allocation, clustered sector allocation, and background garbage ~ h ~ ~ that are key algorithms in solid-state files (SSFs) using flash EEPROMs. Dynamic sector allocation resembles a log-structured file system, which sequentially writes all data modifications to the SSF. Clustered sector allocation is a technique for using the dynamic sector allocation mechani...

As NAND flash memory becomes increasingly popular as data storage for embedded systems, many file systems and database management systems are being built on it. They require an efficient index structure to locate a particular item quickly from a huge amount of directory entries or database records. This paper proposes μ-Tree, a new ordered index structure tailored to the characteristics of NAND...