The effect of gate – drain/source underlap ( Lun ) on a narrow band LNA performance has been studied , in 30 nm FinFET using device and mixed mode simulations. Studies are done by maintaining and not maintaining the leakage current (Ioff) of the various devices. LNA circuit with two transistors in a cascode arrangement is constructed and the input impedance, gain and noise-figure have been used...

Using TCAD modeling, the effect of changing FinFET structure parameters, such as gate stack layer sizes, rib shape, or doping levels, on electrical characteristics device is investigated.

In this study, we analyzed the total ionizing dose (TID) effect characteristics of p-type FinFET and Nanowire FET (NW-FET) according to structural aspect through comparison two devices. Similar n-type devices, NW-FETs are less affected than FinFETs by TID effect. For inverter circuit simulation, both n- p-types NW-FET were regarding The operation considering was verified using Berkeley short-ch...

Abstract Semiconductor qubits have garnered attention in the field of device physics. Owing to limited coherence electrons and holes, smaller more compact are desirable. This requirement is aligned with miniaturization conventional transistors. In this study, we consider a spin qubit based on FinFET (Fin Field-Effect Transistor) by using SPICE (Simulation Program Integrated Circuit Emphasis) si...

Trends in modeling and measurements of the Soft Error Rate (SER) critical charge (Qcrit) for recent generation CMOS SOI devices are reviewed. Modeling and measurements as a function of voltage on 65, 45, 32 and 22 nm planar, SOI devices will be presented. The modeling techniques used will be reviewed and, where possible, compared to experimental measurements. Finally modeling of new device stru...

An effective approach based on a multi-parameter rational fitting technique is proposed to model the microwave small-signal response of active solid-state devices. The model is identified by fitting multibias scattering-parameter measurements and its analytical expression is implemented in a commercial microwave circuit simulator. The approach has been applied to the modelling of a silicon-base...

This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two al...