This paper presents an asynchronous FPGA that combines 4-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. 4-phase dual-rail encoding is employed to achieve small area and low power for function units, while LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters...

As a good trade-off between CPU and ASIC, FPGA is becoming more widely used in both industry and academia. The increasing complexity and scale of modern FPGA, however, impose great challenges on the FPGA placement and packing problem. In this paper, we propose RippleFPGA to solve the packing and placement simultaneously through a set of novel techniques, such as (i) smooth stair-step flow, (ii)...

Future generation embedded multicore will be based on hundreds of processors connected through Network on Chip (NOC) . Design productivity of embedded multicore is a major challenge for the semiconductor industry. In this paper, an automatic very large scale NoC design methodology based on FPGA IP is proposed to accelerate the embedded multicore design productivity using very large scale multi-...

The development of FPGA-based digital signal processing devices has been gaining attention. Researchers seek to reduce power consumption and enhance signal processing quality in these devices with given resources and spatial limits. Hence, there is a need to investigate both the capability and the power consumption associated with the various digital filtering schemes commonly used in FPGA-base...

This paper presents the FPGA implementation of sliding mode control algorithm for bilateral teleoperation, such that, the problem of haptic teleoperation is addressed. The presented study improves haptic fidelity by widening the control bandwidth. For wide control bandwidth, short control periods as well as short sampling periods are required that was achieved by the FPGA. The presented FPGA de...

We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which we can compare. Although the algorithms used are based on previously known approaches, we present several enhancements that improve run-time and quality. We present placement and routin...

This paper describes a structured technique for providing full observability and controllability for functionally debugging FPGA designs in hardware, capabilities which are currently not available otherwise. Similar in concept to flip-flop scan chains for VLSI, our design-level scan technique includes all FPGA flip-flops and RAMs in a serial scan chain using FPGA logic rather than transistor lo...

This paper outlines an FPGA VLSI design methodology that was used to realize a fully functioning FPGA chip in 130nm CMOS with improved routability and memory robustness. The architectural design space exploration and synthesis capability were enabled by the Verilog-to-Routing CAD tool. The capabilities of this tool were extended to enable bitstream generation and deployment. To validate the arc...