In the MPEG-1 multimedia standard, no encoding scheme is defined, but a generally accepted scheme includes the following building blocks: discrete cosine transform, quantization, zig-zag scanning, run-level coding, variable-length encoding, and motion estimation. In this paper, we describe the investigation into how such building blocks can be implemented in reconfigurable hardware, more specif...

The soft computing algorithms are being nowadays used for various multi input multi output complicated non linear control applications. This paper presented the development and implementation of back propagation of multilayer perceptron architecture developed in FPGA using VHDL. The usage of the FPGA (Field Programmable Gate Array) for neural network implementation provides flexibility in progr...

FPGA-based acceleration of molecular dynamics simulations (MD) has been the subject of several recent studies. Here we report on an implementation that we believe to be the first to combine a high-level of FPGA-specific design, systematically determined precision, hardware support for complex force models, and support for simulations of over 250K particles. The target system consists of a stand...

In this paper we present a self con gurable multiplication technique allowing vari able con guration time for a class of LUT based Field Programmable Gate Arrays FPGAs which exist today We show this technique to be implementable on FPGA architectures allowing internally addressable RAM primitives to be directly mapped to the Logic Elements LEs of the logic resource This provides run time read w...

The trend for heterogeneous embedded systems is the integration of accelerators and general-purpose CPU cores on same die. In these integrated architectures, like Zynq UltraScale+ board (CPU+FPGA) that we target in this work, hardware support shared memory low-overhead synchronization between accelerator make case exploring strategies exploit a tight collaboration CPUs accelerator. paper propos...

In this paper, a new VLSI architecture is provided for the application of quad-input and dual-output Fuzzy Logic Controller (FLC) with maximum seven fuzzy membership functions. Our approach is based on classical three stage implementation process – fuzzification, rule inference and defuzzification cores. An innovative design methodology is proposed by splitting the process between DSP processor...

In this paper, we present a video application example and its implementation in a reconfigurable system-onchip (SOC) platform. The proposed platform employs the benefits of field programmable gate array (FPGA) technology. A prototype based on a Xilinx Virtex-5 FPGA is developed. The application includes a video shot boundary detection module based on the local histogram (LH) technique. Diverse ...

In this paper an efficient multiplier-less technique is presented to design and implement a high speed CIC decimator for wireless applications like SDR and GSM. The Cascaded Integrator Comb is a commonly used decimation filter which performs sample rate conversion (SRC) using only additions/subtractions. The implementation is based on efficient utilization of embedded LUTs of the target device ...

This work aims to introduce a design methodology of Time-to-Digital Converters (TDCs) on low cost Field-Programmable Gate Array (FPGA) targets. First, the paper illustrates how to take advantage of the presence of carry chains in elementary logic elements of the FPGA in order to enhance the TDC resolution. Then, it describes how to use the Chip Planner tool to place the partitions composing the...

Robotic fish are ideal for surveying fish resources and performing underwater structural inspections. If a robot is sufficiently fishlike in appearance and does not use a screw propeller, real fish will not be easily surprised by it. However, it is comparatively difficult for such a robot to determine its own position in water. Radio signals, such as those used by GPS, cannot be easily received...