To allow fast communication—at several Gb/s—of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and ca...

The success of system-on-a-chip (SoC) hinges upon a wellconcerted integrated approach from multiple disciplines, such as device, design, and application. From the device perspective, rapidly improving VLSI technology allows the integration of billions of transistors on a single chip, thus permitting a wide range of functions to be combined on one chip. From the application perspective, numerous...

Network-on-Chip (NoC) has recently emerged as an efficient communication solution for the System-on-Chip (SoC) design. Design space exploration and performance evaluation are the most essential task in NoC design. In this paper, an ABC based design space exploration framework for the NoC design is proposed. The objective of the design space exploration is to minimize the total energy consumptio...

In this paper, we propose a new packing strategy to find a free resource for run-time mapping of application tasks to NoC-based Heterogeneous MPSoC. The proposed strategy minimizes the task mapping time in addition to placing the communicating tasks close to each other. To evaluate our approach, a comparative study is carried out for a platform containing single task supported PEs. Experiments ...

Introduction This white paper will highlight the Digital Signal Processor (DSP) based System-onChip (SoC) approach for high-performance wireless Base Stations. TI’s TMS320TCI6488 device will be used as an example to highlight the benefits of a flexible DSP SoC approach for W-CDMA baseband processing. A DSP SoC can provide a single-chip solution, lower power usage, better performance, more fruga...

As the continuing technology scaling keeps increasing the maximum on-chip clock frequency, the demand for the high-speed link that bridges the faster on-chip world and slower off-chip world is rapidly growing. The challenges are stronger than before with more functions being integrated into a single chip, which has become a complicated mixed-mode System on Chip (SoC) design. The performance of ...

Today, IC technology offers the possibility of integrating so many functions onto a single chip that it is indeed possible to implement an “environment-to-environment” system on a single chip. The literature is rich with papers discussing the System-on-Chip (SoC) opportunities; however, there has not been a wide market acceptance for this concept. The basic misconception has been attempting to ...

The physical scaling following Moore’s law is saturated while the requirement on computing keeps growing. The gain from improving silicon technology is only the shrinking of the silicon area, and the speedpower scaling has almost stopped in the last two years. It calls for new parallel computing architectures and new parallel programming methods. Traditional ASIC (Application Specific Integrate...

Systems-on-Chip architecture integrates several heterogeneous components on a single chip. A key challenge is to design the communication between the different entities of a SoC in order to minimize the communication overhead. Network-on-chip (NoC) is a new approach for communication infrastructure of Systems-on-Chip (SoC) design, which provides network based solution for on-chip communication....

The demands of System-on-Chip (SoC) interconnect increasingly cannot be satisjed through the use of a shared bus. A common alternative, using unidirectional, point-to-point connections and multiplexers, results in much greater area requirements and still suffersfrom some of the same problems. This paper introduces a delay-insensitive, asynchronous approach to interconnect over long paths using ...