Table 3: V : power-eecient mapping with min-power t decomp , VI : power-eecient mapping with bh minpower t decomp circuit I II gate delay aver. gate delay aver. Table 1: I : area-delay mapping with conventional decomposition , II : area-delay mapping with minpower t decomp The active cell area is increased by an average of 12.4% while the performance is improved by an average of 1.1%. We have p...

A message transport mechanism which provides highbandwidth low-latency interprocessor communication is the key to the ability of multicomputers to achieve high performance. The system should adapt to changing conditions by routing packets around congested areas and failed links or nodes. We introduce a new message transport mechanism, called Dynamic Virtual Circuits, that combines the best feat...

This study attempted to investigate the impact of teacher’s code-switching on the acquisition of a problematic grammatical structure, namely, object relative clauses, by intermediate EFL learners. Moreover, a secondary objective of the study was to determine the EFL learners’ attitudes and opinions regarding the effectiveness of teacher’s code-switching in their learning of a specific aspect of...

For a multi-domain spoken dialogue system, there are two major difficulties in building its dialogue management. One is to interpret users' interested domain correctly and switch between domains smoothly. The other is the high cost of merging the dialogue management of different application domains. To solve these problems, an implicit domain identification and switching mechanism for dialogue ...

In this paper we present a new memory-efficient scheme for address lookup that exploits the caching support provided by general-purpose processors. We propose Compact Prefix Tries, in which prefixes occurring at multiple levels of a subtrie are compressed into a single node that fits in a single cache line. The scheme performs well in compressing dense as well as sparse tries. For an IP core ro...

In this paper a new switching technique for Direct Torque Control (DTC) fault tolerant induction motor drive is presented, if one inverter leg is completely lost due to such abnormal condition, this system modifies the switching table of DTC system using the available stator voltage vectors in two phase mode with Four Switch Three Phase Inverter (FSTPI) topology to track the stator flux referen...

The direct torque control-space vector modulation (DTC-SVM) is well-known for achieving excellent dynamic overmodulation. However, the method uses complicated predictive stator flux vector control and requires high precision stator flux vector to define overmodulation mode. This paper proposes a straightforward dynamic overmodulation method and constant switching frequency controller without SV...

In this paper Embedded based Z-source multilevel inverter (ZSMLI) is proposed. This work implements a five level cascaded H-bridge Z-source inverter by using embedded control. Switching devices are triggered using embedded controller. In this controller coding is described by using switching table. The presence of Z-source network couples inverter main circuit to the power source that providing...

Humans improve their sport skills by eliminating one recognizable weakness at a time. Inspired by this observation, we define a learning paradigm in which different learners can be plugged together. An extra attention model is in charge of iterating over them and chosing which one to improve next. The paradigm is named Switching Attention Learning (SAL). The essential idea is that improving one...

A compact model for RLC interconnect lines, in the form of a twopath hybrid ladder, is proposed for on-chip interconnect timing and noise analysis. The model parameters are synthesized through constrained nonlinear optimization to directly match the circuit response characteristics over a range of transition times and loads, both at the driving point and at the receiver end. The effect of capac...