The comparison and analysis of SRAM cells provides vital information for trading of design parameters to meet stringent requirements in the deep sub micron ranges. Initially this paper introduces to SRAM cells, then cell parametric dependences are investigated and finally simulation results of the same are shown. An 11T SRAM cell is compared with the conventional 6T SRAM cell for SNM, Power, DR...

Whereas contemporary Error Correcting Codes (ECC) designs occupy a significant fraction of total die area in chipmultiprocessors (CMPs), approaches to deal with the vulnerability increase of CMP architecture against Single Event Upsets (SEUs) and Multi-Bit Upsets (MBUs) are sought. In this paper, we focus on reliability assessment of multithreaded applications running on CMPs to propose an adap...

This paper proposes design of a low power sense amplifier. It is designed for the low power and delay of the circuit by using the variable threshold mos devices. Sense amplifiers are used in the memories to increase the speed for accessing data from different locations. So the speed of data read of SRAM is highly reliable on the design of sense amplifiers. The introduced circuit is tested under...

This paper presents a new 10T SRAM cell that has enhanced read speed along with good read and write stability. While the read access time of the proposed cell is 0.72x and 0.83x smaller as compared to the two most popular 10T SRAM cells at 500C; the read SNM is 1.16x and 1.05x higher compared to existing 10T cells. Though the read-write power of the proposed cell is higher with respect to the e...

Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM). However, the limited data retention time of these dynamic bitcells results in the need for power-consuming periodic refresh cycles. This Letter measures the impact of body biasing as a control factor to improve the retention time of a 2 kb memo...

As the standby supply voltage for the static RAM (SRAM) design scales down for the low-power purpose, the static noise margin of SRAM also decreases. If the supply voltage is below the data retention voltage (DRV), the data need to be checked and corrected before they are sent out of the memory block. In this project, we study the effect of implemented error correction code (ECC) technique to t...

Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a critical component in modern CMOS integrated circuits, novel approaches to addressing these problems are needed. Here, six and seven transistor SRAM cells are presented that do not suffer from reduced stability when read. ...

ABSTRACT: SRAM area is expected to exceed 90% of overall chip area because of the demand for higher performance, lower power, and higher integration. To increase memory density, memory bitcells are scaled to reduce their area by 50% each technology node. High density SRAM bitcells use the smallest devices in a technology, making SRAM more vulnerable for variations. This variation effect the sta...

Read stability has been considered one of the dominant factors governing the overall performance and operation limitation of static random access memory (SRAM). Furthermore, periodic precharge in read/write (R/W) cycle is the major source of power consumption in an SRAM circuit. To address these two concerns, a newly developed SRAM architecture, with specific concentration on read operation, is...