GPUs are now considered as serious challengers for highperformance computing solutions. They have power consumptions up to 300 W. This may lead to power supply and thermal dissipation problems in computing centers. In this article we investigate, using measurements, how and where modern GPUs are using energy during various computations in a CUDA environment.

This paper presents a method based on dual threshold voltage assignment to reduce the leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that the read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. The key idea is thus to realize and depl...

Abstract — In CMOS circuit’s design, as the threshold voltage is reduced due to voltage scaling, it leads to increase in sub-threshold leakage current and hence static power dissipation. In this paper we propose a power reduction technique named transistor gating. In this technique two sleep transistors PMOS and NMOS are inserted in between the supply voltage and ground. A PMOS is inserted in b...

Full adders are important components in applications such as digital signal processing (DSP) architecture, and microprocessors. Over the past decade, several adiabatic logic styles have been reported. This paper deals with the design of a 1-bit full adder using adiabatic logic style (DTGAL), which are derived from static CMOS logic, without a large change. This paper also proposes a new design ...

This paper presents the simulation results of a 4ˆ4-bit array two phase clocked adiabatic static CMOS logic (2PASCL) multiplier using 0.18 —m standard CMOS technology. We also propose a new design of 2PASCL XOR which reduces the number of transistors as well as the power consumption. Analytical method to compare the lower current flow in adiabatic circuit is also presented. At transition freque...

This paper addresses to enhance the stability of8T SRAM bitcell by lowering its leakage power. Scaling down of process parameters such as supply voltage affects the Read ability and Write stability of the cell. As number of transistors on chip increases power dissipation also increases and as a result of this stability of the cell gets affected. This paper aims at reducing the leakage power and...

Continuous scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of integrated circuits. Low power consumption and smaller area are the most important criteria for the fabrication of DSP systems. Static random access memories (SRAMs) consist of almost 90% of very large scale integrated (VLSI) circuits. The ever-increasing demand f...

Static CMOS logic style is often the choice of designers for synthesizing low power circuits. This style is robust in terms of noise integrity however, it offers less speed. Domino logic style, as an alternative is often found in critical paths of various large scale high performance circuits. Yet, due to high switching activity they are not suitable for synthesis of low power circuits. To achi...

The article presents a real-time hardware implementation of a foreground object detection for a non-static camera setup. The system consists of two parts: the calculation of the displacement between two consecutive frames using a correlation based corner tracker and background generation method ViBE (Visual Background Extractor). The paper discusses details of the used hardware modules, resourc...

Abstract. We consider the Bean’s critical state model for anisotropic superconductors. A variational problem solved by the quasi–static evolution of the internal magnetic field is obtained as the Γ-limit of functionals arising from the Maxwell’s equations combined with a power law for the dissipation. Moreover, the quasi–static approximation of the internal electric field is recovered, using a ...