Power dissipation is one of the major concerns of Very Large Scale Integration (VLSI) circuit designs. Leakage power is becoming the dominant power component in deep submicron technology. In this work a new 9T adiabatic SRAM is presented. The elementary cell structure of adiabatic SRAM consists of two high load resistors which are constructed of PMOS, a cross-coupled NMOS pair, NMOS switch whic...

The occupancy of caches has tended to be dominated by the logic bit value ‘0’ approximately 75% of the time. Periodic bit flipping can reduce this to 50%. Combining cache power saving strategies with bit flipping can lower the effective logic bit value ‘0’ occupancy ratios even further. We investigate how Negative Bias Temperature Instability (NBTI) affects different power saving cache strategi...

SRAM cell read stability and write-ability are major concerns in CMOS technologies, due to the progressive increase in VDD and transistor scaling. In this paper, we studied and comparedthe performance of 7TN (with NMOS access transistor), 7TP (with PMOS access transistor) andconventional 6T structure.SRAM cells have been simulated in SPICE with 0.35 μm technology. The techniques that provide th...

The majority of space taken in an integrated circuit is the memory. SRAM design consists of key considerations, such as increased speed, low power and reduced layout area. A cell which is functional at the nominal supply voltage, can fail at a lower voltage. From a system perspective this leads to a higher bit-error rate with voltage scaling and limits the opportunity for power saving. While th...

Recent studies have shown that embedded DRAM (eDRAM) is a promising approach for 3D stacked lastlevel caches (LLCs) rather than SRAM due to its advantages over SRAM; (i) eDRAM occupies less area than SRAM due to its smaller bit cell size; and (ii) eDRAM has much less leakage power and access energy than SRAM, since it has much smaller number of transistors than SRAM. However, different from SRA...

Aggressive scaling of transistor dimensions with each technology generation has resulted an increased integration density and improved device performance at the expense of increased leakage current. Diagnosis is becoming a major concern with the rapid development of semiconductor memories. In this paper, we propose a very low cost Design-forDiagnosis (DfD) solution for design of write driver ci...

1 Research Scholar of Sagar Institute of Research & Technology, Bhopal, Madhya Pradesh, India 2 Professor, Dept. of Electronics and Communication, Sagar Institute of Research & Technology, Bhopal, Madhya Pradesh, India. __________________________________________________________________________________________ Abstract: Scaling of devices in bulk CMOS technology contributes to short channel effe...

In this paper, a hybrid memory architecture based on new array of SRAM and resistive random-access (RRAM) cells is proposed to perform in-memory computing by implementing all basic two-input Boolean functions. The can be configured as dual-purpose element. It used an in mode keep data for high-performance application requirements. also sense amplifier (SA-SRAM) reading the contents RRAMs perfor...

In order to meet all the expectations of consumers, today's technology is equipped with large capacity memories. Additional factors include power consumption and delay, which are crucial in determining how well a gadget performs. Memory an important factor many widgets, as devices get smaller, their size likewise gets less. Every computerized device, result, uses little power, speed utmost impo...

The explosive growth of battery operated devices has made low-power design a priority in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The increasing number of transistor count in the SRAM units and the surging leakage current of the MOS transistors in the scaled technologies have made the SRAM unit a power hungry block from both dynamic and static p...