The present work describes the implementation of a faster converging adaptive filter through the recursive least square algorithm for one dimensional signals denoising such as sinusoidal and audio signals i.e., to obtain an original sinusoidal signal and the audio signal back from the signal which was corrupted using a random noise .The application had been performed over an FPGA (field-program...

In this paper a compact FPGA architecture for the AES algorithm with 128-bit key targeted for low-cost embedded applications is presented. Encryption, decryption and key schedule are all implemented using small resources of only 222 Slices and 3 Block RAMs. This implementation easily fits in a low-cost Xilinx Spartan II XC2S30 FPGA. This implementation can encrypt and decrypt data streams of 15...

This Paper proposes the implementation of multiplier using ancient Indian vedic mathematics (Urdhvatiryagbhyam) that has been modified to improve performance of high speed mathematics, it shows the modified architecture for a 16*16 Vedic multiplier module using Urdhvatiryagbhyam technique. The design implementation is described in both at gate level and high level RTL code using Verilog Hardwar...

Abstaract This paper presents the design of an embedded system for the assistance of persons with handicaps, implemented into the Spartan 3E Starter Board. The unit is defined in VHDL, and it targets a Xilinx Spartan-3E FPGA. Some of the modules are generic and can be easily reused without changes in other designs. The circuit was designed on a Windows XP PC using Xilinx ISE12.3 CAD tool. The m...

este artículo se hace la descripción del diseño de un filtro digital tipo FIR con ocho bits de ancho de datos. Este sistema ha sido implementado en un FPGA (SPARTAN 3E de XILINX) y posee un software que realiza el cálculo de los coeficientes del filtro y la reconfiguración del hardware. Las pruebas se realizaron usando el programa MATHLAB para verificar su funcionamiento. Abstract—This paper pr...