This work describes a reconfigurable 10MS/s to 100MS/s, 0.5V to 1.2V, 0.98mm, 10b low-power 0.13um CMOS two-step pipeline ADC. The SHA employs gate-bootstrapped sampling switches and a two-stage amplifier based on a low-threshold NMOS differential input stage to obtain 10b accuracy even at a 0.5V supply. A signal-isolated all directionally symmetric layout reduces the MDAC capacitor mismatch wh...

In this document we are presenting a new approach to design an optimised Direct Digital Frequency Synthesizer (DDFS) for complex demodulation used in digital receivers. For that, we suggest an adaptation of the phase to sine converter by combining the two following techniques: 1) an optimized COordinate Rotation DIgital Computer (CORDIC) algorithm 2) the principle of Taylor series approximation...

This work presents a low-power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in 180nm silicon-based CMOS process. Simultaneous capacitor sharing and op-amp technique is used between two successive stages of Sample-and-Hold Amplifier (SHA) to reduce the power consumption. The memory effect proposed eliminated by low input capacitance variable gm op-amp. differential integral nonlinearity...

Due to the nonlinear and aliasing effects, sub-Nyquist photonic receiver for radio frequency (RF) signals with large instantaneous bandwidth suffers limited dynamic range noise performance. We designated a deep residual network (Resnet) realize adaptive linearization across 40 GHz bandwidth. In contrast conventional methods, learning method achieves suppression of multifactorial spurious distor...

Sustainability is becoming the main character of financial industry in Europe, especially after Sustainable Finance Disclosure Regulation (SFDR) 2019/2088, which came into force on March 10th, 2021. However, despite top-down indications for disclosing and reporting sustainability practices provided by this new policy, actors still lack a comprehensive framework how to track measure their social...

Direct Digital Synthesis (DDS) systems generate fine frequency resolution signals over a broad spectrum that are used in a wide variety of applications such as multi-mode RF, communications, measurements and test. A high performance DDS band-pass Digital to Analog Converter (DAC) architecture and implementation is presented that delivers high spectral purity over a narrow-band response. The low...

A 10b multibit-per-stage pipelined ADC incorporating merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are ±0.40 LSB and ±0.48 LSB, respectively. The ADC fabricated in a 0.25 μm CMOS occupies 3.6 mm active die area and consumes 208 mW under a 2.5...

Pipelined ADCs are widely used in Nyquist sampling applications that require a combination of high resolution and high throughput. While scaling of CMOS technology offers the potential for improvement of sampling rate, the accompanying reduction in supply voltage creates both fundamental and practical limitations on achievable resolution and speed, particularly when low power consumption is req...