many of the video processing algorithms cannot be implemented in real time on general computers, due to their computational complexity. for an efficient implementation, a custom hardware that can be reconfigured for the algorithm, is used. in this paper a new acceleration hardware based on fpga elements is proposed. this hardware can be adapted with the processing algorithm through fpga design ...

We overcome mismatch constraints of capacitor DAC design in SAR ADCs using a completely reconfigurable DAC with content addressable memory beneath groupings of unit capacitors. We demonstrate a linearity optimization technique in simulation and measurement. We achieve a nearly 2-bit repeatable ENOB improvement with a peak of 11.3 bits.

In this paper we present a novel technique to accelerate reconfigurable video coding with parallel architectures. We focus on the use of the Graphics Processing Unit (GPU) as our platform for parallel processing but the algorithm can be implemented on other parallel architectures. Implementation of the solution shows that execution time is reduced 16-60% depending on the decoder module implemen...

To answer new challenges, systems on chip need to gain flexibility and fpgas need to gain structure. We propose a general framework for SoC architectures and software tools in which different kind of processing units are programmed at high level. We show a reconfigurable unit suitable for this framework and we draw the outline of a supercompiler able to address such an architecture.

This thesis proposes novel methodologies for design, optimisation and generalisation of reconfigurable hardware based finance computation. The applications of the proposed methodologies to numerical methods which are commonly used in the finance industry, such as Monte Carlo and Finite difference are studied in detail. These studies show reconfigurable hardware can effectively improve performan...

MATRIX is a novel, coarse-grain, reconfigurable computing architecture which supports confgurable instruction distribution. Device resources are allocated to controlling and describing the computation on a per task basis. Application-specific regularity allows us to compress the resources allocated to instruction control and distribution, in many situations yielding more resources for datapaths...

MATRIX is a novel, coarse-grain, reconfigurable computing architecture which supports configurable instruction distribution. Device resources are allocated to controlling and describing the computation on a per task basis. Application-specific regularity allows us to compress the resources allocated to instruction control and distribution, in many situations yielding more resources for datapath...

This paper describes an approach for adaptive dynamic instruction set extension, tuning embedded processors to specific applications which are going to be executed in their life-time. These new instructions are generated after production. The processor has two modes: training mode and normal mode. Training mode can be done offline or online. The applicationspecific instructions are extracted fr...