The major problem in wormhole routing networks is related with the contention due to message blocking. Reconfigurable networks are an alternative to reduce the negative effect that congestion produces on the performance of the network. Our work is focused on dynamic reconfiguration. This technique consists basically of placing the different processors in the network in those positions which, at...

This paper studies the difference in computational power between the mesh-connected parallel computers equipped with dynamically reconfigurable bus systems and those with static ones. The mesh with separable buses (MSB) is the mesh-connected computer with dynamically reconfigurable row/column buses. The broadcasting buses of the MSB can be dynamically sectioned into smaller bus segments by prog...

In these days, many dynamically reconfigurable architectures have been introduced to fill the gap between ASICs and softwareprogrammed processors such as GPPs and DSPs. These reconfigurable architectures have shown to achieve higher performance compared to software-programmed processors. However, reconfigurable architectures suffer from a significant reconfiguration overhead and a speedup limit...

We have proposed a new reconfigurable parallel image processing system in which three-dimensional (3D) LSI is used. A new dynamical multi-context reconfiguration scheme is employed in this system. This scheme can decrease the number of instructions between a reconfigurable processing element array and control RISC processor, and also enable efficient execution of various image processing functi...

In this paper, a frequency reconfigurable active array antenna (RAA) system, which can be reconfigurable at three different frequency bands, is proposed. The proposed RAA system is designed with a novel frequency reconfigurable front-end amplifiers (RFA) with the simple reconfigurable impedance matching circuits (RMC) with the MEMS switches. With the MEMS switch, the RFA is realized without any...

Conventional FPGA design assumes a one-to-one mapping between circuits and device resources. In contrast, dynamically reconfigurable designs map many circuits to shared device resources. Each many-to-one mapping can be decomposed into sequences of temporal, one-to-one mappings. The verification of dynamically reconfigurable logic is complicated by the need to verify that each constituent mappin...

While reconfigurable computing has traditionally involved attaching a reconfigurable fabric to a single processor core, the prospect of large-scale CMPs calls for a reevaluation of reconfigurable computing from the perspective of multicore architectures. We present ReMAPP, a reconfigurable architecture geared towards application acceleration and parallelization. In ReMAPP, parallel threads shar...

A primary impediment to wide-spread exploitation of reconfigurable computing is the lack of a unifying computational model which allows application portability and longevity without sacrificing a substantial fraction of the raw capabilities. We introduce SCORE (Stream Computation Organized for Reconfigurable Execution), a streambased compute model which virtualizes reconfigurable computing reso...

Reconfigurable computing is an emerging field in this modern world of computer and electronics engineering, which allows the system hardware to be changed periodically in order to execute different applications on the same hardware. Partial reconfiguration is the prerequisite of reconfigurable computing, as it allows time-sharing of physical resources for the execution of multiple design module...

A new FPGA architecture (reconfigurable datapath architecture, rDPA) for word-oriented datapaths is presented, which has been developed to support a variety of Xputer architectures. In contrast to von Neumann machines an Xputer architecture strongly supports the concept of the “soft ALU” (reconfigurable ALU). Fine grained parallelism is achieved by using simple reconfigurable processing element...