This paper enumerates a low power, high speed design of flip-flop having less number of transistors. In flip-flop design only one transistor is being clocked by short pulse train which is known as True Single Phase Clocking (TSPC) flip-flop. The true single-phase clock (TSPC) is common dynamic flip-flop which performs the flip-flop operation with little power and at high speeds. In this paper, ...

Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance ...

This paper discusses a rail to rail swing, mixed logic style 1-bit 28-transistor (28T) full-adder, based on a novel architecture. The performance metrics: power, delay, and power delay product (PDP) of the proposed 1-bit adder is compared with other two high performance 1-bit adder architectures reported, till date. The proposed 1-bit adder has a 50% improvement in delay, and 49% improvement in...

In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay pr...

– A novel circuit topology for the CMOS based Incrementer/Decrementer circuit is presented in this paper. The design methodology is extensively based on Domino logic and it utilizes a simple two level look-ahead structure. The highly parallel, regular structure of the proposed 8-bit decision module (DM) macro cell makes this design, especially advantageous for constructing higher order versions...

In this chapter we have discussed the research work done on the basis of literature review and study. The research methodology and the techniques to modify the present designs in order to achieve better performance have been discussed with their merits and demerits. In this paper FS-SERF and HSSERF full adder topologies are presented. The analysis of Power, Delay, Power Delay Product (PDP) opti...

With the advancement of technology, power consumption and higher speed becomes major concern for VLSI systems. In this paper, a new hybrid domino XOR is proposed and compared with existing domino XOR cell. As an application of proposed XOR cell, 1-bit full adder has been designed and compared with a full adder circuit using existing XOR cell. Both proposed designs XOR and full adder show better...

The Maximum Likelihood Estimator (MLE) and Extended Quasi-Likelihood (EQL) estimator have commonly been used to estimate the unknown parameters within the joint modeling of mean and dispersion framework. However, these estimators can be very sensitive to outliers in the data. In order to overcome this disadvantage, the usage of the maximum Trimmed Likelihood Estimator (TLE) and the maximum Exte...