Software oriented techniques to hide memory latency in superscalar and superpipe2ined machines include loop unrolling, software pipelining, and software cache prefetching. Issuing the data fetch request prior to actual need for data allows overlap of accessing with useful computations. Loop unrolling and software pipelining do not necessitate microarchitecture or instruction set architecture ch...

High-level synthesis is the process of translating a high-level program like specification of the behavior of a digital circuit into a structural design in terms of interconnected set of P..egisterTransfer level components. Component selection and pipelining (CS&P) is one of the important problems in HLS. The time complexity of the exhaustive search algorithm for this problem is exponential. In...

Parallelizing compilers do not handle loops in a satisfactory manner. Fine-grain transformations capture irregular parallelism inside a loop body not amenable to coarser approaches but have limited ability to exploit parallelism across iterations. Coarse methods sacriice irregular forms of parallelism in favor of pipelining (overlapping) iterations. In this paper we present a new transformation...

Coarse Grain Reconfigurable Arrays (CGRAs) offer improved energy efficiency and performance over conventional architectures. However, the limitations of modulo counter oriented execution on these devices restricts their broader application. This paper introduces the Offset Pipelining execution model and an associated scheduling algorithm to address these limits. The proposed approach broadens t...

Software pipelining is an eecient instruction scheduling method to exploit the multiple instructions issue capability of modern VLIW architectures. In this paper we develop a precise mathematical formulation based on ILP (Integer Linear Programming) for the software pipelining problem for architectures involving structural hazards. Compared to other heuris-tic methods as well as an ILP-based me...

The clock frequency of a synchronous circuit can be increased at the expense of increased system latency, area, and power using synchronous optimization techniques such as pipelining and retiming. Pipelining is a well developed methodology, having been applied to almost every computer architecture from microprocessors to supercomputers. Retiming, on the other hand, has only recently become popu...

EEcient resource usage is a key to achieve better performance in parallel database systems. Up to now, most research has focussed on balancing the load on several resources of the same type, i.e. balancing either CPU load or I/O load. In this paper, we present oating probe, a strategy for parallel evaluation of pipelining segments in a shared-everything environment that provides dynamic load ba...

In recent years a new category of data analysis applications have evolved, known as data pipelining tools, which enable even nonexperts to perform complex analysis tasks on potentially huge amounts of data. Due to the complex and computing intensive analysis processes and methods used, it is often neither sufficient nor possible to simply rely on the increase of performance of single processors...