Phase Retrieval is the task of reconstructing a signal x ∈ Cn up to a phase from intensity measurements. In [1] it was shown that m ≥ 4n− 2 generic intensity measurements suffice to discriminate any two signals in Cn up to a phase. With a similar approach this result was slightly improved to m ≥ 4n− 4 in [8] 1. The bound m ≥ 4n− 4 is known to be close to optimal. More precisely, by relating pha...

This paper presents a methodology to determine all-digital phase-locked loop (ADPLL) circuit variables based on required design specifications, including output phase noise, fractional spur and locking time. An analytical model is developed to characterize the effects of different noise sources on ADPLL output phase noise and fractional spur. Applying the proposed noise model, circuit variables...

This paper presents a complete noise analysis of a ΣΔ-based fractional-N phase-locked loop (PLL) based frequency synthesizer. Rigorous analytical and empirical formulas have been given to model various phase noise sources and spurious components and to predict their impact on the overall synthesizer noise performance. These formulas have been applied to an integrated multiband WLAN frequency sy...

An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm and consumes 88 μW at 0.4-V supply for...

Zero Crossing Digital Phase Locked Loop with Arc Sine block (AS-ZCDPLL) is used to linearize the phase difference detection, and enhance the loop performance. The loop has faster acquisition, less steady state phase error, and wider locking range compared to the conventional ZCDPLL. This work presents a Zero Crossing Digital Phase Locked Loop with Arc Sine block (ZCDPLL-AS). The performance of ...

A phase-locked loop (PLL) angular modulator scheme has been proposed which has the characteristics of wideband modulation frequency response. The modulator design is independent of the PLL closed-loop transfer function H(s), thereby allowing independent optimization of the loop's parameters as well as the modulator's parameters. A phase modulator implementing the proposed scheme was built to ph...

This article proposes a family of phase-locked loop schemes based on sliding modes. The use mode algorithms ensures fast response and global stability. In particular, two new are presented, both complex framework for representing three-phase signals. compares the obtained with traditional schemes, faster is when modes used. Additionally, as an application example, algorithm combined complex-coe...

The additive noise response of a charge pump phase-locked loop in the synchronous mode of operation has been studied. In order to determine the tracking and noise performances of the loop, mean square values of tracking error and local oscillator phase jitter have been analytically obtained. Analytical results agree well with the simulation results obtained here and elsewhere [3]. The analysis ...