Multipliers are one of the most important building blocks in processors. This paper describes a low-power 32×32-bit parallel multiplier, designed and fabricated using a 0.13 μm double-metal doublepoly CMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor logic circuits, without significantly compromising the speed performance of the ...

New VLSI circuit architectures for addition and multiplication modulo (2n 1) and (2n + 1) are proposed that allow the implementation of highly efficient combinational and pipelined circuits for modular arithmetic. It is shown that the parallel-prefix adder architecture is well suited to realize fast end-around-carry adders used for modulo addition. Existing modulo multiplier architectures are i...

The Galois/Counter Mode of Operation (GCM), recently standardized by NIST, simultaneously authenticates and encrypts data at speeds not previously possible for both software and hardware implementations. In GCM, data integrity is achieved by chaining Galois field multiplication operations while a symmetric key block cipher such as the Advanced Encryption Standard (AES), is used to meet goals of...

Multiplication is a commonly used operation of Digital signal processing. The objective of a good multiplier is to provide a physically compact, high speed and a low power consuming chip. A low power multiplier using a dynamic range determination unit and a modified upper/lower left-to-right in the partial product summation is designed. The proposed multiplier is based on the modified booth alg...

This article presents a Lagrange multiplier-based adaptive droop control to mitigate distribution power loss of parallel-connected distributed energy resource (DER) systems in dc microgrids. The comprising line and converter can be modeled as quadratic function the output currents DER systems, which optimized by tertiary-layer multiplier method obtain optimal current references for secondary-la...

This work presents a scalable digit-parallel finite field polynomial multiplier architecture with digit size of 32 bits for NIST-standardized binary elliptic fields. First, dedicated is proposed each recommended by NIST, i.e., 163, 233, 283, 409 and 571. Then, having support all variants fields curves proposed. For performance investigation, we have compared architectures design. After this, th...