In this paper, we analyze the gain from simultaneous sizing of driving buffers and routing switches on an FPGA interconnect performance. We show that it is not area feasible to build FPGAs with optimally sized interconnects. However, with constrained interconnect area, it is possible to significantly improve the speed of interconnects by simultaneously sizing the driving buffers and routing swi...

The unified logical effort (ULE) model for delay evaluation and minimization in paths composed of CMOS logic gates and resistive wires is presented. The method provides conditions for timing optimization while overcoming the limitations of standard logical effort (LE) in the presence of interconnects. The condition for optimal gate sizing in a logic path with long wires is also presented. This ...

Transistor sizing is very important for determination of the circuit performance. As a result for providing fair evaluation, an optimal size of transistor is necessary. Genetic algorithm that is capable of reduction of search problem complexity uses the transistor sizing which is originally a kind of search problem in the large multidimensional search space for energy consumption optimization. ...

this paper presents a probabilistic confidence-interval based method for optimal placement of shunt capacitors in distribution networks by considering probabilistic characteristics of loads. the main objective function are reducing loss and improving the voltage profile. backward forward sweep method has been employed to obtain the power flow results in distribution system. in addition, integer...

design and expansion of distribution systems seems inevitable in view of the need to satisfy the rise in energy consumption in a technical and economical way. optimal location, sizing and determining the service area of substations is one of the principle problems in expansion of distribution systems. also uncertainty is one of the important factors that increase risk of exact decision makings....

We address a multi-item capacitated lot-sizing problem with setup times, stock and demand shortages. Demand cannot be backlogged, but can be totally or partially lost. Safety stock is an objective to reach rather than an industrial constraint to respect. In this paper we consider an approach based on a lagrangean relaxation of the capacity constraints to generate a lower bound of the optimal va...

This paper proposes an inverse lot-sizing model for eliciting the cost parameters (the setup, holding, and backlog costs) of a supplier from earlier demand vs. optimal lot-size pairs. It is assumed that the supplier solves a single-item, multi-period, uncapacitated lot-sizing problem with backlogs to optimality to calculate its lot-sizes, and the buyer is aware of this fact. The inverse optimiz...

Non-stationary stochastic lot sizing problem appears in many industrial environments where demand is nonstationary and stochastic, and replenishments require fixed freight fees. This paper presents the cost performance assessment of three inventory control strategies proposed for the stochastic lot sizing problem, namely Hua et al. (2008)’s strategy (HYHX), Tarim and Kingsman (2006)’s model (TK...

In this paper we study sensitivity analysis of the uncapacitated single level economic lot-sizing problem, which was introduced by Wagner and Whitin about thirty years ago. In particular we are concerned with the computation of the maximal ranges in which the numerical problem parameters may vary individually, such that a solution already obtained remains optimal. Only recently it was discovere...

Subthreshold CMOS logic can be used to provide energyefficient computation in scenarios where performance is not a critical concern. Analysis in existing literature, and explored in this work, demonstrates that the use of minimum-sized devices can offer the greatest energy-efficiency, but in the face of variation, upsizing schemes must be considered to reduce gate failure rates. We explore the ...