We propose a new decoder based on a generalized confidencescore. The generalized confidence score is defined as a product of confidence scores obtained from confidence information sources such as likelihood, likelihood ratio, duration, duration ratio, language model probabilities, supra-segmental information etc. All confidence information sources are converted into confidence scores by a confi...

Traditional error correcting decoder is designed according to specific algorithm, which is a reverse course of encoding. In this paper, a novel general neural network decoder is proposed in the form of symmetrical self-organizing map (SSOM), which can achieve decoding function to any error correcting codes. The SSOM decoder is tested by decoding low-density parity-check (LDPC) code. The perform...

This paper presents a novel Random Neural Network (RNN) based soft decision decoder for block codes. One advantage of the proposed decoder over conventional serial algebraic decoders is that noisy codewords arriving in non binary form can be corrected without rst rounding them to binary form. Another advantage is that the RNN, after being trained, has a simple hardware realization that makes it...

In this paper, we study and analyze the computational complexity of a software-based H.264/AVC baseline profile decoder. Our analysis is based on determining the number of basic computational operations required by a decoder to perform the key decoding subfunctions. The frequency of use of each of the required decoding subfunctions is empirically derived using bitstreams generated from two diff...

The likelihood decoder is a stochastic decoder that selects the decoded message at random, using the posterior distribution of the true underlying message given the channel output. In this work, we study a generalized version of this decoder where the posterior is proportional to a general function that depends only on the joint empirical distribution of the output vector and the codeword. This...

Because of their excellent error-correcting performance, low-density parity-check (LDPC) codes have recently attracted a lot of attention. In this paper, we are interested in the practical LDPC code decoder hardware implementations. The direct fully parallel decoder implementation usually incurs too high hardware complexity for many real applications, thus partly parallel decoder design approac...

Ultra high-speed block turbo decoder architectures meet the demand for even higher data rates and open up new opportunities for the next generations of communication systems such as fiber optic transmissions. This paper presents the implementation, onto an FPGA device of an ultra high throughput block turbo code decoder. An innovative architecture of a block turbo decoder which enables the memo...