نتایج جستجو برای: multiprocessor interconnection network

تعداد نتایج: 683678  

2004
Hashem Hashemi Najaf-abadi Hamid Sarbazi-Azad

The OTIS-hypercube is an optoelectronic architecture for interconnecting the processing nodes of a multiprocessor system. In this paper, an empirical performance evaluation of the OTIS-hypercube is conducted for different traffic patterns and routing algorithms. It is shown that, depending on the traffic pattern, minimal path routing may not have the best performance and that adaptivity may be ...

2006
Harsh Sadawarti

Annotation: Two pass routing scheme is described for communication in a multiprocessor system employing a unique-path multistage interconnection network in the presence of faults in the network. It is capable of tolerating all single faults and many multiple faults in all except the first and last stages of the network. The routing scheme is useful for tolerating both permanent as well as inter...

1999
Shi Baw Roger D. Chamberlain Mark A. Franklin Ch'ng Shi Baw

This paper presents the design and initial analysis of an optically interconnected multiprocessor based on the use of VCSELs (Vertical Cavity Surface Emitting Laser) and free-space optical interconnects.The design is oriented to applications where the performance is bandwidth limited in conventional multiprocessors. The processor interconnection network is based on a physical ring topology whic...

2006
Gene Eu Jan Shao-Wei Leu Cheng-Hung Li Xiaoshe Dong

A simple yet efficient algorithm was presented by Jan and Huang recently to distribute loads evenly on multiprocessor computers with hypercube interconnection networks. That algorithm was developed based on the well-known dimension exchange method. However, the error accumulation suffered by other algorithms based on the dimension exchange method is avoided by exploiting the notion of regular d...

Journal: :IEEE Trans. Computers 1990
Ming-Syan Chen Kang G. Shin Dilip D. Kandlur

family of 6-regular graphs, called hexagonal meshes or H-meshes, is considered n H as a multiprocessor interconnection network. Processing nodes on the periphery of a-mesh are first wrapped around to achieve regularity and homogeneity. The diameter of a wrapped H-mesh is shown to be of O(p), where p is the number of nodes in the 1/2 o t H-mesh. An elegant, distributed routing scheme is develope...

1990
Ishfaq Ahmad Arif Ghafoor

In this paper, we propose a semi distributed approach, for load balancing in large parallel and distributed systems. The proposed scheme is a two level hierarchical scheme which partitions the interconnection structure of a multiprocessor system into independent symmetric regions. We consider interconnection structures belonging to the classical infinite families of distance transitive graphs. ...

2003
Jeonghee Shin Timothy Mark Pinkston

Routing algorithms are traditionally evaluated under Poisson-like traffic distributions. This type of traffic is smooth over large time intervals and has been shown not necessarily to be representative to that of real network loads in parallel processing and communication environments. Bursty traffic, on the other hand, has been shown to be more representative of the type of load generated by m...

Journal: :J. Inf. Sci. Eng. 2002
Sung Woo Chung Jeong-Heon Shin Hyong-Shik Kim Chu Shik Jhon

The cache replacement policy is one of the most important factors that affect the cache performance. With the trend of increasing associativity in second-level caches, implementing an efficient replacement algorithm becomes more important than just eliminating conflict misses. The LRU cache replacement algorithm has been known to work well in a single processor system by reducing the cache miss...

Journal: :J. Parallel Distrib. Comput. 2013
Alexey L. Lastovetsky

Heterogeneity is one of the most profound and challenging features of today’s parallel and distributed computing systems. From the macro level, where networks of distributed computers, composed by diverse node architectures, are interconnected with potentially heterogeneous networks, to themicro level,where deeper memory hierarchies, heterogeneousmulticores, and various accelerator architecture...

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