CRC is significantly more efficient in hardware than software; consequently, you can improve the throughput of your system by implementing a hardware accelerator for CRC. In addition, by eliminating CRC from the tasks that the processor must run, the processor has more bandwidth to accomplish other tasks. Figure 8–1 illustrates a system in which a Nios® II processor offloads CRC processing to a...

In recent years, with the development of processor architecture, heterogeneous processors including Center processing unit (CPU) and Graphics (GPU) have become mainstream. However, due to differences core, system is now facing many problems that need be solved. order solve these problems, this paper try focus on utilization efficiency core design some reasonable resource scheduling strategies. ...

Originally developed by the consortium Sony-Toshiba-IBM for the Playstation 3 game console, the Cell Broadband Engine processor has been increasingly used in a much wider range of applications like HDTV sets and multimedia devices. Conforming the new Cell Broadband Engine Architecture that extends the PowerPC architecture, this processor can deliver high computational power embedding nine cores...

Faculty of Electrical Engineering, Mathematics and Computer Science CE-MS-2012-05 A streaming application like software defined radio (SDR) executed on a heterogeneous multi-processor system on chip (MPSoC) consists of various transceiver jobs that have to be scheduled on different processors concurrently. The hard real time performance requirements of these jobs can be guaranteed on the multi-...

Scheduling problems that involve distance constrained tasks with repetitive requests are enjoying an increase in popularity in real time system design. Timing constraints defined by periods of fixed lengths for each task enforce some frequency of task execution. Alternatively deadlines could be specified relatively to the finish time of the previous execution of the same task. Hence, the schedu...

Chip Multi-Processors (CMPs) are now available in a variety of systems and provide the opportunity for achieving high computational performance by exploiting applicationlevel parallelism. In the communications environment, network processors (NPs) are often designed around CMP architectures and in this context the processors may be used in a pipelined manner. This leads to the issue of scheduli...

A communication subsystem consists of protocol tasks and operating system mechanisms that support the configuration and execution of protocol stacks composed of protocol tasks. To parallelize a communication subsystem effectively, careful consideration must be given to the threading architecture. The threading architecture binds processing elements with the protocol tasks and the messages assoc...

Synchronization of task usually happens in real-time embedded systems. But it is not easy to achieve a good performance for the synchronization tasks, especially on multicore processor. After analysis of the task characteristics on homogeneous multicore processor, we proposed a Longest Synchronization-Point Time (LSPT) task scheduling algorithm to obtain the good real-time performance and the m...

We are interested in scheduling tasks from several selfish agents on a set of parallel identical machines. A coordination mechanism consists in giving a scheduling policy to each machine. Given these policies, each agent chooses the machines on which she assigns her tasks, and her aim is to minimize the average completion times of her tasks. The aim of the system (social cost) is to minimize th...