SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are limited to radix-2 and radix-4. Higher radix dividers are therefore formed by a combination of low-radix stages. In this paper, we present an analysis of the effects of radix-2 and radix-4 SRT divider ...

SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are limited to radix-2 and radix-4. Higher radix dividers are therefore formed by a combination of low-radix stages. In this paper, we present an analysis of the effects of radix-2 and radix-4 SRT divider ...

This paper is focused on how to implement a nonlinear voltage divider used in the electrical power network disturbances measurement system preconditioning circuit. The voltages acquired from the electrical power network have amplitudes between 0.2 kV and 10 kV, values which are very high for an acquisition board. These amplitudes must be reduced to the values accepted by the acquisition boards:...

This paper presents the design and simulated performance of an ultra-low-power 4/5 frequency divider based on a CMOS ring oscillator. The divider operates over a 189% locking range (29MHz – 1GHz) for both division ratios, covering the MICS band and 433MHz and 915MHz ISM bands while consuming only 3.3 μW in MICS band. The wide locking range and low power consumption makes this very suitable for ...

In this paper, we present a new design of a compact tri-band unequal power divider, which is composed of a circularcoupling power divider and a triple-band resonator. The unequal power dividing characteristic is realized by two circular shaped microstrip lines coupled through a circular shaped slot. The triple-band resonator, which comprises a conventional half-wavelength resonator, a short stu...

An ultra-low power injection locked frequency divider (ILFD) is presented and demonstrated. Based on a 5-stage single ended ring oscillator, the ILFD achieves a lock range of 56% at a division ratio of 5 in the medical implant communications service (MICS) and the 433MHz ISM frequency bands. The ILFD is implemented in a 90nm CMOS process. It consumes 3 μW of power from a 1.0V supply and 100 μm ...

An 8-bit programmable square finder cum frequency divider architecture is presented. This special architecture includes a high speed parallel counter, clock trigger circuit, eight bit multiplier logic, sequence termination logic and sequence restarter logic. The entire architecture is divided into two parts: The frequency divider section and the square finder section. The frequency divider circ...

In this paper design and simulation of a 4.3 – 5.4 GHz LC digitally controlled oscillator (LC DCO) in IBM 7RF 0.18μm CMOS technology are presented. Wide gigahertz tuning range is achieved by using two LC DCOs, sharing same structure. DCO is made of one NMOS negative impedance transistor pair and LC tank, which consists of high quality inductor and two switched capacitor arrays for coarse and fi...

a power divider (pd)/ power combiner (pc) with high quality factor and enhanced output ports isolation using substrate integrated waveguide (siw) technology is proposed. an siw cavity is designed to provide a high quality factor filtering response and an smd resistor is attached between two output ports to realize the high isolation. the value of the applied resistor is calculated by using the ...