In this paper, various designs of low-power full-adder cell are studied. Simulation of these full-adder cells are carried out. The experiments simulate all combinations of input transitions and consequently determine the power consumption for the various full-adder cells. The simulation results highlight the weaknesses and the strengths of the various full-adder cell designs. The high performan...

The aim of paper is to get over the problem of 6T SRAM cell where it loses its reliability at low supplies due to degraded noise margins. These is done by using a 10T SRAM where the cell uses a charge sharing technique between the transistors so that SRAM could be made more rigid against the noises that can cause damage to the cell at low power supplies and along with that charge sharing betwee...

A design of 8 bits, 2.5V pipeline ADC is introduced in this paper. The comparator is the main improvement aiming at realizing low power dissipation. The latched comparator is adopted to achieve the specification. The design is implemented under 0.25um CMOS technology which achieves a power dissipation of 205.9mW.

Sequential Optimization for Low Power Digital Design

This paper presents an improved power quality converter (IPQC) based power supply design for high brightness Light Emitting Diode (HB-LED) low power lighting. The IPQC circuit uses a Cuk buck-boost converter to operate it in discontinuous conduction mode (DCM) using voltage follower technique for the mitigation of harmonic contents present in the AC mains current. Subsequently reduction in harm...

In order to achieve a longer battery life suppression of energy consumption is vital. A demand for design methods for less energy consumption is increasing. The subthreshold scaling can reduce energy per cycle significantly by the scaling of supply voltage (VDD) below threshold voltage (Vth). Threshold voltage of CMOS technology represents the value of the gate-source voltage when the current i...

A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital fi...

This paper addresses the challenge of controlling power dissipation in the microprocessor domain. System level power management architectures [I] have helped control chip-set and peripheral power substantially. But the consequence is that the CPUs are now the power limiters, especially in the mobile domain. This paper addresses two challenges in power reduction of high-performance CPUs. First w...

This paper summarizes the utility of some low-power design (LPD) methods based on architectural and implementation modifications, for FPGA based systems. Power consumption is becoming one of the mayor design trade-off in today electronic. In this work, the contribution of spurious transitions to the overall consumption is evidenced and main strategies for its reduction are analyzed. Empirical r...

Abstract Before signals of a digital circuit reach steady state gates can have multiple transitions Since the power is dissipated in a CMOS circuit mainly due to transitions the extra transitions increase power consump tion These transitions are the hazard pulses generated by logic gates when signals arrive by paths of varying de lays The maximum width of a hazard pulse produced by a gate is th...