A 1.2 V, 0.61 mA bias current, low noise amplifier (LNA) suitable for low-power applications in the 2.4 GHz band is presented. Circuit has been implemented, laid out and simulated using a UMC 130 nm RF-CMOS process. The amplifier provides a 13.3 dB power gain a noise figure NF< 2.28 dB and a 1-dB compression point of −15.69 dBm, while dissipating 0.74 mW. Such performance make this design suita...

Deep-brain stimulation (DBS) is an emerging research topic aiming to improve the quality of life patients with brain diseases, and a great deal effort has been focused on development implantable devices. This paper presents low-noise amplifier (LNA) for acquisition biopotentials DBS. electronic module was designed in low-voltage/low-power CMOS process, targeting applications. The measurement re...

This article introduces a design of Low Noise Amplifier (LNA), for the field diamond particle detectors. amplifier is described from simulation to measurements, which include pulses {\alpha} particles detection. In hadron therapy, with high-frequency pulsed beams, detector promising candidate beam monitoring and time-stamping, prerequisite fast electronics. The LNA designed surface mounted comp...

A K-band CMOS broadband low noise amplifier (LNA) based on the magnetically coupled resonator (MCR) matching network technique is presented and implemented in 0.13-µm technology. Such LNA consists of two common-source (CS) pseudo-differential stages, which use capacitive neutralization to enhance inversion isolation Gain. The MCR-based input achieves good balance loss performance by inventing a...

A low-power 435-MHz single-ended low-noise amplifier was implemented in a 0.35-μm silicon on insulator (SOI) CMOS technology. The SOI CMOS LNA has a simulated noise figure of 0.6 dB, input 1-dB compression point of –12.5 dBm, input thirdorder intercept point of –5 dBm, and small-signal gain of 22 dB. Total power dissipation is 10 mW from a 2.5-V supply. LNA chip area is 1.4 mm x 0.58 mm. Due to...

This work presents a 2.4 GHz low noise amplifier (LNA) for wireless sensor network in CMOS 0.13-μm Silterra process. The forward body bias technique with cascode configuration has been adopted in order to implement a suitable LNA for low power consumption target. The supply voltage was varied from 0.4 V to 0.6 V as to optimize the tradeoffs for LNA performances. The simulation results show that...

This paper describes a high-gain CMOS low-noise amplifier (LNA) for 2.4/5.2-GHz WLAN applications. The cascode LNA uses an inductor at the common-gate transistor to increase its transconductance equivalently, and therefore it enhances the gain effectively with no additional power consumption. The LNA is matched concurrently at the two frequency bands, and the input/output matching networks are ...

ETRI Journal, Volume 29, Number 5, October 2007 ABSTRACT⎯An ultra-wideband low-noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18-μm CMOS process and adopts a twostage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input-impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are m...

In this paper, a CMOS Multi-band LNA using High-Q active inductors load with a binary code band selector suitable for multi-standards wireless applications is proposed. Using an improved high-Q active inductor including two bits binary controlled code, the multi-band low noise amplifier operating at four different frequency bands is realized. The proposed amplifier is designed in TSMC 0.18-um C...