The design of a I-input and a ?-input 4-valued logic gate is described. These gatcs can be used to implement cells of a gate array, with the benefit of having prograrnriiabk functionality and multiple-valued logic input and output lincs. Programmable fimctionality allows any or the four billion functions of a '-input 4-valued logic gate to be implemented by thc samc cell, and multiplc-valucd hg...

This paper presents a combined fault detection and discrimination strategy for CMOS logic incorporating active resource mitigation and monitoring. The approach is demonstrated for a NOR gate using a dual redundant gate design with selective mitigation and analogue or digital detection. The potential benefits of the approach are discussed with respect to resource awareness and management within ...

A very large-scale logic simulation engine "VELVET" has been developed VELVET is a vectorized event-driven simulator which can handle simultaneously both gate-level logic and Register-Transfer Level structure. VELVET can process simulation jobs two orders of magnitude faster than a conventional gate-level simulator. This paper describes how to realize such high performance, an algoritha for vec...

We experimentally demonstrate and characterize a four-qubit linear-optical quantum logic circuit. Our robust and versatile scheme exploits encoding of two qubits into polarization and path degrees of single photons and involves two crossed inherently stable interferometers. This approach allows us to design a complex quantum logic circuit that combines a genuine four-qubit C(3)Z gate and severa...

|While estimating glitches or spurious transitions is challenge due to signal correlations, the random behavior of logic gate delays makes the estimation problem even more difcult. In this paper, we present statistical estimation of signal activity at the internal and output nodes of combinational and sequential CMOS logic circuits considering uncertainty of gate delays. The methodology is base...

A fine-grained reconfigurable architecture based on double gate technology is presented. The logic function operating on the first gate of a double gate (DG) transistor is reconfigured by altering the bias on its second gate. A compact reconfigurable cell is proposed that merges two stacked 3-state resonant tunneling devices and non-silicon transistors and “hides” the cost of reconfiguration by...

JIN, YAWEI. Simulation Methodology to Compare Emerging Technologies for Alternatives to Silicon Gigascale Logic Device. (Under the direction of Dr. D. W. Barlage). Practical realization of low-power, high-speed transistor technologies for future generation nano-electronics can be achieved with novel structures, such as FinFET, tri-gate or with the integration of exotic channel materials, such a...

Reversible circuits find applications in many areas of Computer Science including Quantum Computation. This paper examines the testability of an important subclass of reversible logic circuits that are composed of k-wire controlled NOT (kCNOT with k -CNOT gate can be implemented using an irreversible k-input AND gate and an EXOR gate. A reversible k-CNOT circuit where each k-CNOT gate is realiz...

We report the first realization of a biomolecular AND gate function with double-sigmoid response (sigmoid in both inputs). Two enzyme biomarker inputs activate the gate output signal, which can then be used as indicating liver injury, but only when both of these inputs have elevated pathophysiological concentrations, effectively corresponding to logic-1 of the binary gate functioning. At lower,...

This paper investigates the relationship between a single-electron gate probability of failure and the random variations affecting its elements. The study focuses on digital logic gates and circuits. Two major implementations are considered: static complementary logic gates and threshold logic gates (TLG). In addition to implementation, the effect of the gate fan-in on the reliability is invest...