The core of a parallel processing system is the interconnection network by which the system’s processors are linked. Due to the great role played by the interconnection network’s topology in improving the parallel processing system’s performance, various topologies have been proposed in the literature. This paper proposes a new interconnection network topology, referred to as the chained-cubic ...

In this paper, the formation control of networks of multiple agents is studied via controllability, where the network is under leader-follower structure with some agents taking the leader role and others being followers interconnected via neighbor-based rule. It is shown that the controllability of a multi-agent system is uniquely determined by the topology structure of interconnection graph, a...

Intellectual property (IP) core-to-node mapping is an important but intractable optimization problem in Network-on-Chip (NoC) application design. In this paper, we present an approach to map cores onto hierarchical NoC architecture which consists of two levels. The top-level interconnection network is realized by a 2D mesh of communicating routers, and a tree based topology is used at the secon...

Based on a model of a parallel vector computer with a shared memory, its scalability properties are derived. The processor-memory interconnection network is assumed to be composed of crossbar switches of size b œ b. This paper analyzes sustainable peak performance under optimal conditions, i.e., no memory bank conflicts, sufficient processor-memory bank pathways, and no interconnection network ...

Shrinking process node sizes allow the integration of more and more functionality into a single chip design. At the same time, the mask costs to manufacture a new chip increases steadily. For the industry this cost increase can be absorbed by selling more chips. Furthermore, new innovative chip designs have a higher risk. Therefore, the industry only changes small parts of a chip design between...

The reliability and cost are two important performance measures of an interconnection network. Both these aspects need to be attended at the layout design stage for an appropriate trade-off between them. This paper introduces a new approach for layout optimization of interconnection networks using dynamic programming. Our principal objective here is to optimize the network layout so as to maxim...

A reconfigurable parallel architecture whose interconnection topology can be dynamically modified in order to match the communication characteristics of a given algorithm provides flexibility for efficient execution of various applications. But, due to communication links switching devices design constraints, connecting a large number of processors on a dynamically programmable interconnection ...

The design of an interconnection network and switch architectural design are significantly influenced by contemporary supercomputer technology. As technology evolves, its impact on interconnection network needs to be reevaluated and elaborated. In this paper we have traced the path in this direction and addressed performance analyses of a high speed 4x4 switch design and interconnect network in...

How do different QoS (Quality of Service) mechanisms affect the resource and quality allocations over the interconnection of the future Internet? What will be the consequences on the economics of interconnection and its settlements? These are important questions that arise with the evolution of the Internet as a network of QoS networks that support a variety of performance requirements. The con...