Fast High-Order Variation-Aware IC Interconnect Analysis. (August 2007) Xiaoji Ye, B.E., Wuhan University Chair of Advisory Committee: Dr. Peng Li Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verifica...

The off-chip electrical interconnects for high speed and high I/O processors have become increasingly complex and costly. Data transfer rates exceeding gigabits per second are common in high performance computer systems. A cost-effective wide-band interconnect between chips, modules, boards, backplane, frames and cabinets has become increasingly critical in the system design. This paper reviews...

For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to ...

The objective of this work is to provide simple, e cient, yet reasonably accurate interconnect performance estimation models for synthesis and design planning under various complex interconnect optimization techniques. We have developed a set of closed-form delay estimation models as functions of interconnect length as well as some other key interconnect and device parameters with the considera...