This paper designed a tapped delay line Time-to-Digital Converter(TDC) based on 0.18μm CMOS, there is total level 128 voltage-controlled delay line.The symmetric delay phase-locked loop is used to increase the stability of delay chain and reduce the system clock’s skew and jitter. The simulation results show that : when the voltage is 1.8V, and the reference clock frequency is 250MHz, the least...

Article history: Received 14 June 2017 Received in revised form 8 August 2017 Accepted 8 August 2017 Available online xxxx

PURPOSE The purpose of this study was to identify the relationship between aniseikonia scores in the vertical and horizontal meridians and the foveal microstructure on vertical and horizontal spectral-domain optical coherence tomography (SD-OCT) in patients with idiopathic epiretinal membrane (ERM). METHODS All patients (n = 65) with unilateral ERM were examined, and the aniseikonia scores in...

some areas of ramsar, a city in northern iran are among the world’s wellknown inhabited areas with highest levels of natural radiation. annual exposure levels in these areas are up to 260 mgy y‐1 and the mean exposure rate is about 10 mgy y‐1 for a population of about 2000 residents. if elevated levels of natural radiation as high as a few hundred msv per year is detrimental to health and leads...

A blind identification based algorithm for calibration of pipelined ADC is discussed in this paper. In contrast to traditional approaches that use one highly precise input stimulus to characterize the device, the approach adopted here is based on providing multiple inputs with nonlinearities of separated spectrum to the device-under-test (DUT). A correction code for each output of ADC is determ...

A time-to-digital converter, using a charge pump to translate time interval into charge and a SAR-ADC quantizing the charge, can achieve sub-picosecond resolution. To improve the linearity and area occupation, we propose a sampling method and a layout pattern for the capacitive DAC in the SAR-ADC. The prototype chip was fabricated in 65nm CMOS. The measured DNL and INL are -0.6/0.8 ps and -2.56...

Varadhan’s integration theorem, one of the corner stones of large-deviation theory, is generalized to the context of capacities. The theorem appears valid for any integral that obeys four linearity properties. We introduce a collection of integrals that have these properties. Of one of them, known as the Choquet integral, some continuity properties are established as well.

An 8 bit segmented current steering DAC is presented for the compensation of mismatch of sensors with current output arranged in a large arrays. The DAC is implemented in a 1.8 V supply voltage 180 nm standard CMOS technology. Post layout simulations reveal that the design target concerning a sampling frequency of 2.6 MHz is exceeded, worst-case settling time equals 60.6 ns. The output current ...

BACKGROUND/AIMS To characterise the extension and progression of alteration of neurosensory layers following acute and chronic branch retinal artery occlusion (BRAO) in vivo using spectral-domain optical coherence tomography. METHODS In this observational case series, eight eyes with acute BRAO and nine eyes with chronic BRAO were analysed using a Spectralis Heidelberg Retina Angiograph (HRA)...

Besides being a marker of various somatic stem cells in mammals, prominin-1 (CD133) plays a role in maintaining the photoreceptor integrity since mutations in the PROM1 gene are linked with retinal degeneration. In spite of that, little information is available regarding its distribution in eyes of non-mammalian vertebrates endowed with high regenerative abilities. To address this subject, prom...