In this paper, five new multiplexer-based architectures for 1 -bit full adder circuit designs are proposed. Following these architectures, various full adder circuits can be built through different circuit implementations of multiplexers. For instance, in this paper, we demonstrate that by substituting each multiplexer with two transmission gates, a set of new full adder circuits are ready to b...

Parallel-prefix adders (also known as carrytree adders) are known to have the best performance in VLSI designs compared to that of conventional Ripple Carry Adder (RCA). However, each type of parallel prefix adder has its own pros and cons and are chosen according to the design requirement of the application. This paper investigates mainly two types of carry-tree adders, the brent kungg adder a...

Quantum addition circuits are considered being of two types: (1) Toffoli-adder which use only classical reversible gates (controlled-not and Toffoli), (2) QFT-adder based on the quantum Fourier transformation. We present a systematic translation QFT circuit into Toffoli-based adder. This result shows that has fundamentally same fault-tolerance cost (e.g., T count) as most cost-efficient Toffoli...

   Quantum-dot Cellular Automata (QCA) technology is a solution for implementation of the nanometer sized circuits and it can be a suitable replacement for CMOS. Similar to CMOS technology, designing the basic computational element such as adder with the QCA technology is regarded as one of the most important issues that extensive researches have been done about it. In this paper, a new eff...

We construct logical gates via topology optimisation (aimed to solve a station problem of heat conduction) of a conductive material layout. Values of logical variables are represented high and low values of a temperature at given sites. Logical functions are implemented via the formation of an optimum layout of conductive material between the sites with loading conditions. We implement and and ...

Reversible logic has extensive applications in quantum computing, it is a unconventional form of computing where the computational process is reversible, i.e., time-invertible. The main motivation behind the study of this technology is aimed at implementing reversible computing where they offer what is predicted to be the only potential way to improve the energy efficiency of computers beyond v...

The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and microprocessor data path units. As such, extensive research continues to be focused on improving the power delay performance of the adder. This paper proposes a new method for implementing a low power full adder by means of a set of Gate Diffusion Input (GDI) cell based multipl...

Multiple constant multiplication scheme is the most effective common sub expression sharing technique which is used for implementing the transposed FIR filters. Ripple carry operation allows adder tree to minimize hardware cost, unfortunately it detriment timing and gives low speed operation. To outperform this high speed adder is proposed and analyzed for real time speech signal applications. ...

This paper presents a 372ps 64-bit adder using Fast Pull-up Logic (FPL) in 0.18 μm CMOS technology. Fast Pullup Logic is devised and applied to decrease pull-up time which is critical in domino-static adder. The implemented adder measures the worst case delay of 372ps. The adder has a modified tree architecture using Load Distribution Method and has 6 logic stages.

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adde...