This paper presents a transceiver that uses a 4-bit flash analog-to-digital converter (ADC) for the receiver and an 8-bit current-steering digital-to-analog converter (DAC) for the transmitter. The 8-GSamples/s converters are 8-way time interleaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6 LSB, improves the accuracy of the interleaved sampling clocks...

This paper presents a transceiver that uses a 4-bit flash ADC for the receiver and an 8-bit current-steering DAC for the transmitter. The 8-GSa/s converters are 8-way time interleaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6 LSB, improves the accuracy of the interleaved sampling clocks to within 10 ps, and reduces systematic coupling noise to less t...

Abstract Pt100 is a resistance temperature detector characterized by relatively linear resistance/temperature relationship in narrow range. However, the sensor shows certain degree of static transfer function nonlinearity 4.42 % range between −200 °C and 850 °C, which unacceptable for some applications. As solution to this problem, mixed-mode linearization method based on special dual-stage pie...

A 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A nonresetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effec...

This paper proposes a 4-b 5-GS/s time-based flash ADC in 45-nm digital CMOS technology, which utilizes both rising and falling edges of the clock for sampling and quantiza-tion. A dual-edge-triggered scheme reduces the dynamic power consumption of a voltage-to-time converter and the clock buffers by half. We doubled both the reset and the available regeneration times by interleaving the time co...

A new method enabling the use of stationary non-linear signals has been proposed for testing the linearity of high resolution ADCs. With this method, linearity requirement of the source can be dramatically relaxed and faster sources can be utilized to reduce the test time and increase test coverage for the ADC. Preliminary simulation results show that with a 5-bit linear input signal, the trip ...

Pipeline ADCs are becoming popular at high speeds and with high resolution. This paper discusses the options of number of bits/stage conversion techniques in pipelined ADCs and their effect on Area, Speed, Power Dissipation and Linearity. The basic building blocks like op-amp, Sample and Hold Circuit, sub converter, DAC, Residue Amplifier used in every stage is assumed to be identical. The sub ...