In order to fully utilize the instruction level parallelism of VLIW DSP processors, DSP programs have to be optimized by software pipelining. Software pipelining has been studied for many years and widely implemented in optimizing compilers. However, due to the rearrangement of the original instructions, it is often very difficult to re-use or port the code of a software-pipelined loop to other...

Profound knowledge of the interaction between algorithms and digital signal processor (DSP) architectures is required to be able to efficiently design complex communications equipment. Whereas both algorithms and architecture find treatment in many courses individually, education focusing on design methodology for DSP implementation is found to be rare. This contribution describes a concept and...

In real-life, embedded devices like mobile phone, notebook computers are made use of RISC processor and DSP .In Digital Signal Processing (DSP) applications the critical operations usually involve many multiplications and/or accumulations. So, for real time signal processing, the high speed multiplier accumulator (MAC) unit is always a key element to achieve a high-performance digital signal pr...

This paper presents the design and implementation of a new Program Address Generator (PAG) unit, which is a part of Program Control Unit (PCU) well suited for DSP Processors. This would be compatible with DSP56002 (DSP Processor from Motorola) at instruction level. The PAG provides hardware dedicated to support loops, which are frequent constructs in DSP algorithm. The proposed architecture of ...

This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operatio...

This paper describes a high-performance scalable SIMD digital signal processor (DSP) developed for multifunctional printer systems. The DSP supports a variable number of datapaths to cover a wide range of performance and maintain a RISC-like pipeline structure. Many special instructions suitable for image processing algorithms are included in the DSP. Quad/dual instructions are introduced for 8...

Today's DSP designers until recently were faced with the task of coding increasingly complex applications using inefficient compilers or tedious handgenerated assembly code. To make matters worse the products demanded low cost, extremely high performance and low power especially in the area of wireless communications and consumer markets. This paper examines the architectural features of severa...

In this paper, we present a basic model for describing hardand software of heterogeneous multi-DSP systems. The software part consists of a task model that has been tuned to suit typical, cyclic DSP applications. Hardware is described by a processor model adapted to multi-DSP systems with point-to-point communication structure, which also includes an exact model of communication timing behavior...

Diminishing performance gains in conventional architectures are driving modern architectures to exploit parallelism more effectively. Next-generation architectures hold promise in the Digital Signal Processing (DSP) arena where high performance and power efficiency are equally important. To better identify optimization techniques on these emerging new architectures, we optimized and evaluated a...

Abstract Aiming at the network characteristics of a smart substation redundant with complex communication messages, large amount interactive data, and high real-time performance, test model multiple submachines in High-Availability Seamless Redundancy (HSR) loop is analyzed. The requirements packet types, size, transmission speed are evaluated, hardware solution based on multi-core Digital Sign...