The p-i-n carbon nanotube (CNT) devices suffer from low ON/OFF current ratio and small saturation current. In this paper by band bending engineering, we improved the device performance of p-i-n CNT field effect transistors (CNTFET). A triple gate all around structure is proposed to manage the carrier transport along the channel. We called this structure multi-segment gate (MSG) CNTFET. Band to ...

The rapid scaling of integrated circuit requires further shrinkage of lateral device dimension, which correlates with pillar thickness in vertical structure. This paper investigates the effect of pillar thickness variation on vertical double gate MOSFET (VDGM) fabricated using oblique rotating ion implantation (ORI) method. For this purpose, several scenarios of silicon pillar thickness tsi wer...

The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at source-channel region is proposed and modeled this paper. gate oxide TFET stacked configuration high-k over low-k to improve control without any lattice mismatches. Tangent Line Approximation (TLA) method used here model accurately. validated by...

This work explores homo- and heterojunction tunnel field-effect transistor (TFET)-based NAND NOR logic circuits using 30 nm technology compares their performance in terms of power consumption propagation delay. By implementing homojunction TFET-based circuits, it has been observed that consumes less than the gate since current drawn by PTFET pull-up network is higher. The delay lower due to its...

The manipulation of the electron spin degree of freedom is at the core of the spintronics paradigm, which offers the perspective of reduced power consumption, enabled by the decoupling of information processing from net charge transfer. Spintronics also offers the possibility of devising hybrid devices able to perform logic, communication, and storage operations. Graphene, with its potentially ...