Introduction: The development of designs for test techniques continue to receive a great deal of consideration [l]. Techniques based on scan is one of the most effective methodologies and has been adopted widely in the area of digital integrated circuit design. When testing systems with scan design, the entire scan registers (SRs) andor combinational modules are always active during the whole s...

Abstract Digital-to-analog converters are crucial building blocks for telecommunication applications. For this kind of applications, the traditional static performance requirements do not apply. The dynamic performance is of the greatest importance. This paper discusses the aspects of the performance of CMOS digital-to-analog converters and models the influence of non-idealities of circuit comp...

In this paper we investigate SET devices from the logic design perspective, using the SET tunnel junction’s ability to control the transport of individual electrons. We introduce a modified turnstile circuit with clock and enable control signals, which has built-in memory and reset functionality. Using the modified turnstile circuit as a building block, we propose a scheme for an n-input digita...

Unlike the classical deterministic digital circuit analysis, we consider the analysis of digital circuits with uncertain inputs. Thus, given a binary function of n uncertain input binary variables, we introduce a new way of using K-maps to express the probability of this binary function in terms of the probabilities of the corresponding input binary variables. This in turn, allows us to estimat...

In this contribution, a design space exploration of the various possible schemes for all-digital symbol timing adjustment of QAM signals is made. The exploration is guided by both performance degradation and implementation cost considerations. The BER performance degradation is obtained using a quasi-analytic simulation approach, while the implementation cost is estimated by high level digital ...

This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers ...

AbstractIn this paper, the use of Simulated Evolution (SimE) Algorithm in the design of digital logic circuits is proposed. SimE algorithm consists of three steps: evaluation, selection and allocation. Two goodness measures are designed to guide the selection and allocation operations of SimE. Area, power and delay are considered in the optimization of circuits. Results obtained by SimE algorit...

Subthreshold source-coupled logic (STSCL) is a logic family that contains a constant bias current in each logic gate. Logic operation is based on the steering of this current towards one of two load resistors using subthreshold dierential pairs. STSCL was proposed for its low power consumption due to the small voltage signal swing, as well its suitability for congurable circuits. In this work, ...

Due to substantial mixed analog-digital circuit integration in one chips CMOS digital imager cannot be considered only as a photoelectric transducer. In this paper, we have identzjied timing and circuit layout considerations that are critical for implementing a digital CMOS camera-on-a-chip. An optimized binaryscaled tree-topology power routing has been shown to be critical for minimizing chip ...