The effects that I/O circuits have on the overall system performance are becoming more and more pronounced nowadays, as many digital processors reached GHz frequency range while I/O operates only up to MHz range. Extensive studies have been done on I/O signal processing and multi-clocking schemes to increase number of bits per Hz of transmission. In this paper, a circuit level approach to this ...

In this paper, a digitally re-configurable Single Input Multi Output voltage mode multifunctional biquadratic analog filter has been presented. The circuit realizes a Single Input Multi Output filter with non-inverting High Pass, Band Pass and Low Pass outputs and employs four Differential Voltage Current Conveyor blocks and uses seven passive components which are two grounded capacitors and fi...

Low-voltage low-power comparators implemented in standard digital processes are of increasing importance in different integrated applications. In this paper a 1-V fully-differential lowpower MOSFET-only comparator with rail-to-rail input swing is presented which can be suitably used in very low-voltage lowpower pipelined A/D converters. This comparator utilizes a resistive divider configuration...

We present exact analytical results for the differential conductance of a finite Kitaev chain in an N-S-N configuration, where topological superconductor is contacted on both sides with normal leads. Our are obtained Keldysh nonequilibrium Green's function technique, using full spectrum without resorting to minimal models. A closed formula linear given, and procedure obtain transport mediated b...

The harmonic in distribution systems becomes an important problem due to an increase in nonlinear loads. This paper presents a new approach based on a graph algorithm for optimum placement of passive harmonic filters in a multi-bus system, which suffers from harmonic current sources. The objective of this paper is to minimize the network loss, the cost of the filter and the total harmonic disto...

In this paper we present novel ultra-low-voltage and high-speed CMOS NAND and NOR gates. For supply voltages below 500mV the delay for an ultra-low-voltage NAND2 gate is approximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch are much lesser than for conventional CMOS. Differential domino gates for AND2/NAND2 and OR2/NOR2 operation are presented. Ul...

This paper presents a new metaheuristic algorithm called BAT search Algorithm (BAT). The BAT search algorithm is used to solve Optimal Power Flow (OPF) problem with the Thyristor Controlled Series Capacitor (TCSC). The TCSC is used to reduce the transmission line losses and improve the voltage profile of the power system. The effectiveness of the BAT Algorithm has been tested for various bus sy...

This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time. In the proposed transmitter, the required tol...

We investigate the impact of surface defect density on the transport properties of molecular beam epitaxy grown InGaAs/AlInAs Quantum Cascade (QC) structures. We examine six parameters of the current–voltage (IV) characteristics of the QC mesas: turn-on voltage, turn-on current density, turn-on differential resistance, differential resistance, cut-off voltage, and cut-off current density. The a...

To provide a quality and secured power supply in all the load centres is a challenging task. Due to the increase in load and various emergency conditions the voltage level in load centres may vary beyond the acceptable level which leads to voltage collapse and increase the system losses. To maintain the voltage levels within the acceptable range in all load centres reactive power support is ver...