A 13-bit, 1.4-MS/s, sixth-order cascaded sigma–delta modulator oversampling at 16 X is implemented in a 0.72 m complementary metal–oxide–semiconductor process for use in the baseband path of a radio-frequency receiver. The modulator achieves 77 dB of dynamic range and dissipates 81 mW from a 3.3 V supply. It is characterized for the blocking and intermodulation requirements of a cordless teleph...

This paper presents a 1.2 GHz continuous time 6 order band-pass Sigma Delta Analog to Digital modulator in IBM 0.18 um CMOS technology. Traditional RLC circuits, with spiral inductors as resonators, were replaced with active inductor based resonators with negative impedance circuits to enhance the quality factor, reduce chip area and eliminate post processing needs. Simulink and Cadence simulat...

Three-phase pwm voltage source inverters are widely employed in high performance ac drive system, active filters and uninterrupted power supply (UPS) etc.For these applications, the converter should provides good dynamic response. However the performance of the converter system largely depends on the accuracy of the applied current control strategy. The current controllers can be classified as ...

Abdelghani Dendouga, Nour-Eddine Bouguechal, Souhil Kouda and Samir Barra Advanced Electronic Laboratory, Batna University, Algeria 05 Avenue Chahid Boukhlouf, 05000 BATNA, ALGERIE E-mail: [email protected] Abstract—Sigma delta modulators (ΣΔMs) form part of the core of today’s mixed-signal designs. The ongoing research on these devices shows the potential of ΣΔ data converters as a promi...

An advanced design methodology using a combination of behavioral models and transistor level models is presented in this paper. This methodology is very interesting for complex mixed-signal IC design, reducing the simulation time and improving the design flexibility. In order to validate the methodology proposed, a High-Speed Bandpass Continuous-Time Delta-Sigma Modulator is modeled. This modul...

This chapter proposes a novel design methodology for a Multi-stAge noise SHaping (MASH) digital delta–sigma modulator (DDSM) which employs multi-moduli. The structure is termed the MM-MASH. The adequacy and benefit of using such a structure is demonstrated. In particular, the sequence length is lengthened if the quantizer modulus of the first-order error feedback modulator (EFM1) of each stage ...

Enhancement of the performance and speed of the Digital Signal processing processors are the major challenge due to its wide spread real world applications. At the same time high quality (less erroneous) and high speed digital inputs are required for these DSP Processors. Hence the high performance and high speed A/D or D/A converter design is the another major issue for performance and speed m...

frequency 40MHz with 78dB Dynamic Range in a 0.35µm CMOS process. I. INTRODUCTION Oversampling bandpass A/D is widely used because of its increased accuracy and decreased analog front-end circuitries in transceiver systems. High frequency digital processing is more robust than its analog counterpart, and does not have the analog circuit imperfections. Digital IF extraction is also very benefici...

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of L th-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no ov...

This paper describes an analog-to-digital converter which combines multiple delta–sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta–sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta–sigma modulators in parallel with no ove...