We experimentally investigate the RF linewidth and timing jitter over a wide range of delay tuning in a self-mode-locked two-section quantum dash lasers emitting at ~ 1.55μm and operating at ~ 21 GHz repetition rate subject to single and dual optical feedback into gain section. Various feedback conditions are investigated and optimum levels determined for narrowest linewidth and reduced timing ...

The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in largearea time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0:13 μm CMOS process. On each of the six analog channels, PSEC4 employs a switched capacitor array (SCA) of 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with...

In this paper, we propose an efficient scheme for side peak cancelation in binary offset carrier (m,n) (BOC(m,n)) with integer modulation order. The proposed scheme reduces significantly the width of the main peak of the auto-correlation function (ACF) and thus the range of influence of the multipath (MP) in BOC-modulated signals. It is based on the use of reference ACFs like that of ideal pseu...

High-speed signaling is very sensitive to jitter. As signals toggle faster and faster, tighter restrictions fall on the signal transmitter and receiver. In many high-speed data applications, the clock edge must fall within a tight margin of time to capture data correctly. The more jitter in a system, the more often the clock edge will fall outside the margin. The frequency of clock edge deviati...

The input frequency limit of the conventional zero-crossing digital phase-locked loop (ZCDPLL) is due to the operating time of the digital circuitry inside the feedback loop. A solution that has been previously suggested is the introduction of a time delay in the feedback path of the loop to allow the digital circuits to complete their sample processing before the next sample is received. Howev...