In modern VLSI design, interconnection delay dominates the circuit delay due to its heavy downstream capacitance. Buffer insertion is a widely used technique for splitting a long wire into several buffered wire segments for circuit performance improvement. In this paper, we investigate buffer insertion issues in structured ASIC design style. We design the layout for two dedicated buffers and ex...

In modern VLSI design, interconnection delay dominates the circuit delay due to its heavy downstream capacitance. Buffer insertion is a widely used technique for splitting a long wire into several buffered wire segments for circuit performance improvement. In this paper, we investigate buffer insertion issues in structured ASIC design style. We design the layout for two dedicated buffers and ex...

We present new design and analysis techniques for the synthesis of parallel multiplier circuits that have smaller predicted delay than the best current multipliers. In [4], Oklobdzija et al. suggested a new approach, the Three-Dimensional Method (TDM), for Partial Product Reduction Tree (PPRT) design that produces multipliers that outperform the current best designs. The goal of TDM is to produ...

In this paper a new approach for minimizing glitches in the combinational parts of static CMOS circuits is presented. Delay balancing is applied in order to guarantee synchronously arriving signal slopes at the inputs of the logic gates. Thus, glitching can be avoided. The delay of a logic gate depends directly on the transistor sizes, i.e. the channel-widths and -lengths (W and L). Specific va...

This paper introduces a new design of penternary inverter gate based on graphene nanoribbon field effect transistor (GNRFET). The penternary logic is one of Multiple-valued logic (MVL) circuits which are the best substitute for binary logic because of its low power-delay product (PDP) resulting from reduced complexity of interconnects and chip area. GNRFET is preferred over Si-MOSFET for circui...

The electronic industry has grown vastly in recent years, and researchers are trying to minimize circuits delay, occupied area and power consumption as much as possible. In this regard, many technologies have been introduced. Quantum Cellular Automata (QCA) is one of the schemes to design nano-scale digital electronic circuits. This technology has high speed and low power consumption, and occup...

A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 μ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold times of I/O registers or buffers. The frequency lock range of the DLL is 150-600 MHz (4x). The DLL uses a combined phase detector and charge pump circuit (PD+CP) for increased speed and reduced jitter. The DLL also em...

Process Variation has become a crucial challenge on both interconnect delay and reliability of nanometer integrated circuit designs. Furthermore, the dramatic increase of power consumption and integration density has led to high operating temperature. Temperature, as well as electromigration (EM) and power, also significantly affects the delay and reliability of interconnects. Considering proce...

In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing as to guarantee synchronously arriving signal slopes at the input of logic gates, thereby avoiding glitches. Since the delay of logic gates depends directly on transistor sizes, their variation allows to equalize different path delays without influencing the total delay of the circuit. Unfortuna...

Efficient and accurate delay calculation is very important in physical design, optimization and fast verification. In this paper we consider explicit delay calculation for RC interconnects with coupling capacitance. The formulae are derived using a simplified transfer function which offers enough accuracy. We have expressed coefficients of two pole transfer function in terms of circuit paramete...