In recent years, different instruction set extensions for cryptography have been proposed for integration into general-purpose RISC processors. Both public-key and secret-key algorithms can profit tremendously from a small set of custom instructions specifically designed to accelerate performance-critical code sections. While the impact of instruction set extensions on performance and silicon a...

despite the extensive deployment of multi-core architectures in the past few years, the design and optimization of each single processing core is still a fresh field in computing .on the other hand, having a design procedure (used to solve the problems related to the design of a single processing core )makes it possible to apply the proposed solutions to specific-purpose processing cores .the i...

The paper presents an implementation of a custom extension of commercially available NIOS processor embedded into Altera reconfigurable hardware. Added true random number generator uses recently proposed principle based on reconfigurable on-chip analog PLLs that are embedded in all modern Altera devices. Proposed solution significantly improves security of System on a Programmable Chip (SOPC) e...

indubitably, the efficacy of metalinguistic awareness in improving efl learners’ grammatical knowledge and writing quality has long been an area of great interest in applied linguistics brown (2001). accordingly, the main objective of the present study was to investigate the impact of planned and unplanned focus on form instruction on students’ ability to learn grammar and use it appropriately ...

This paper proposes a 32-bit RISC-V microprocessor for the IoT, which consists of Hummingbird e203 and configurable precision COordinate Rotation Digital Computer (CORDIC) coprocessor. Coprocessor is used to enhance processing power system. Custom instructions are added original instruction set accelerate complex calculations. Experimental results demonstrate that coprocessor can process applic...

This paper presents our ongoing work on the analysis and optimization of cryptanalytic time-memory tradeoffs targeting the COPACOBANA architecture [KPP06] as platform for the precomputation/online phase.