Determining the means by which an attacker may compromise a given system is the main purpose of vulnerability assessment. As such, there are several models currently in place to track vulnerabilities. Some models focus on the susceptibility of a computer system as a whole where other models track attack paths through a network. This paper proposes a model which accomplishes both. The primary fo...

Process variation reduces a pipeline’s maximum attainable frequency by creating unbalance in the stage delays. As a result, the pipeline ends up cycling with a period close to that of the slowest pipeline stage. ReCycle was proposed in ISCA 2007 as a framework for comprehensively applying cycle time stealing to balance the stage delays under process variation, thereby allowing the pipeline to c...

Abstract:The VLSI design industry has grown rapidly during the last few decades. The complexity of the applications increases day by day due to which the area utilization increases. The tradeoff between area and speed is an important factor. The main focus of continued research has been to increase the operating speed by keeping the area and memory utilization of the design as low as possible. ...

Leapfrog Technology is defined within this project as a holistic, cost effective approach to combining and applying innovative yet simple products and processes concurrently throughout various departments including engineering, fabrication shops, and production stages of construction. The present technology for designing, manufacturing, and installing equipment foundations and systems is labor ...

Program activity graphs can be constructed from timestamped traces of appropriate execution events. Information about the activities on the k longest execution paths is useful in the analysis of parallel program performance. In this paper, four algorithms for finding the near–critical paths of program activity graphs are presented and compared, including an efficient new algorithm that utilizes...

Given an FPGA that has failed to meet its timing specification, techniques are proposed to efficiently diagnose the cause of the faulty behavior. An initial list of suspect configuration logic blocks (CLBs) and interconnects is generated using six-valued fault-free simulation and critical path tracing. The initial list of suspects is then reduced by exploiting the reconfigurability of an FPGA. ...

In this paper we present the FPGA implementation of a new word{serial CORDIC processor working with variable precision. It has been designed in such a way that it allows us to take advantage of the successive shifts in the coordinates involved in the CORDIC algorithm. This signiicatively reduces the total number of cycles required. Special attention has been paid to the design of the critical p...

This paper presents a new scheme for the hardware evaluation of elementary functions, based on a piecewise second order minimax approximation. The novelty is that this evaluation requires only one small rectangular multiplication. Therefore the resulting architecture combines a small table size, thanks to second-order evaluation, with a short critical path: Consisting of one table lookup, the r...

The traditional PERT (Program Evaluation and Review Technique) model uses beta distribution as the distribution of activity duration and estimates the mean and the variance of activity duration using “pessimistic”, “most likely” and “optimistic” time estimates proposed by an expert. In the past several authors have modified the original PERT estimators to improve the accuracy. In this paper, on...