Verification has become one of the major bottlenecks in today’s circuit and system design. Up to 80% of the overall design costs are due to checking the correctness. Formal verification based on Bounded Model Checking (BMC) is a very powerful method that allows to prove the correctness of a device. In BMC the circuits behavior is considered over a finite time interval, but for the user it is of...

We present a hybrid method for verification and synthesis of parameterized self-stabilizing protocols where algorithmic design and mechanical verification techniques/tools are used hand-in-hand. The core idea behind the proposed method includes the automated synthesis of self-stabilizing protocols in a limited scope (i.e., fixed number of processes) and the use of theorem proving methods for th...

Quantum communication is a rapidly growing area of research and development. Quantum cryptography has already been implemented for secure communication, and commercial solutions are available. The application of formal methods to classical computing and communication systems has been very successful, and is widely used by industry. We expect similar benefits for the verification of quantum syst...

Functional verification consumes more than 70% of the labor invested in today’s SoC designs. Yet, even with such a large investment in verification, there’s more risk of functional failure at tapeout than ever before. The primary reason is that the design team does not know where they are, in terms of functional correctness, relative to the tapeout goal. They lack a functional verification map ...

Placing guarantees on a program’s correctness is as hard as it is essential. Several approaches to verification exist, with testing being a popular, if imperfect, solution. The following is a formal description of QuickCheck finite state automata, which can be used to model a system and automatically derive command sequences over which properties can be checked. Understanding and describing suc...

We present Kopitiam, an Eclipse plugin for certifying full functional correctness of Java programs using higher-order separation logic. Kopitiam extends the Eclipse Java IDE with an interactive environment for program verification, powered by the general-purpose proof assistant Coq. Moreover, Kopitiam includes a development environment for Coq theories, where users can define program models, an...

Business transactions are prone to failure and to deal with unexpected situations some specification languages, e.g. StAC, introduce notions like compensation handling. Given the importance of verification of correctness in business related software, it is important to fill in the gap between specification languages like StAC and the verification software

Series-parallel poset verification is a powerful methodology for proving the design correctness of complex systems and protocols. In this paper we use series-parallel posets to model and verify the behavior of a distributed transmission protocol with multiple senders and receivers. The verification is carried out with the SPPV environment.

With increasing design complexity, verification becomes a more and more important aspect of the design flow. Modern circuits contain up to several million transistors. In the meantime it has been observed that verification becomes the major bottleneck, i.e. up to 80% of the overall design costs are due to verification. This is one of the reasons why recently several methods have been proposed a...

Web Services have been widely used in Service-Oriented Architecture (SOA) framework. Due to the complexity of interactive behaviors, formal verification plays a critical role in Web services-based application engineering. In this paper, we mainly use Live Sequence Chart Specifications (LSC) to specify the complex behaviors among multiple Web services, and then translate LSC to automata model EL...