Hepatitis C virus (HCV) is a global health care problem. Diagnosis of HCV infection is mainly based on the detection of anti-HCV antibodies as a screening test with serum samples. Recombinant immunoblot assays are used as supplemental tests and for the final detection and quantification of HCV RNA in confirmatory tests. In this study, we aimed to compare the HCV core antigen test with the HCV R...

This paper presents an offline/online concurrent scan based built-in-self-test (scan-BIST) method for a Network-onChip (NoC) based SoC. The proposed architecture contains a special scan cell and an Embedded Test Core (ETC) as its test source. The ETC performs a static flow control and a centric average power consumption control during the proposed test mechanism. To reduce the test vector traff...

Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of such core-based ICs, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illus...

As part of an industry wide effort IEEE is in the process of standardizing the elements of test technology such that plug & play can be achieved when testing SoC designs. This standard under development is a language namely, Core Test Language (CTL), which is introduced in this paper. CTL describes all necessary information for test pattern reuse and the needs of test during system integration....

This tutorial responds to the rapidly increasing use of various cores for implementing systems-on-a-chip. It specifically focusses on processor cores. We will give some examples of cores, including DSP cores and application-specific instructionset processors (ASIPs). We will mention market trends for these components, and we will touch design procedures, in particular the use compilers. Finally...

test challenge. Vendors of intellectual property cores usually give no information about a core’s internal logic (in other words, it is a black box). As a result, system designers cannot perform traditional test generation processes such as automatic test pattern generation (ATPG) and fault simulation. Instead, the core vendor specifies a set of test vectors that must be applied to the core to ...

In the Reconfigurable System-On-a-Chip (RSOC), an FPGA core is embedded to improve the design flexibility of SOC. In this paper, we demonstrate that the embedded FPGA core is also feasible for use in implementing the proposed hybrid pattern Built-In Self-Test (BIST) in order to reduce the test cost of SOC. The hybrid pattern BIST, which combines Linear Feedback Shift Register (LFSR) with the pr...