A 2-digit higher radix analog-to-digital converter (ADC) circuit consisting of a combination of a pipelined ADC and a set of cascaded current comparator cell has been proposed. The ADC generates multi-valued logic outputs rather than the conventional binary output system. The design is implemented using 0.25μm CMOS process. The performance analysis of the design shows desirable performance para...

| This paper investigates online testing for fault localization in CMOS circuits using IDD waveform analysis. The methods investigated in this paper are applicable both to static as well as dynamic CMOS circuits. We show that not only can IDD waveform analysis detect a number of defects that are otherwise undetectable by IDDQ testing, it can also be applied to online testing and diagnosis of CM...

A new dynamic differential logic family, Short-Circuit Current Logic (SCL), is proposed for low-power high-performance applications. It achieves low-power consumption by using an aggressively reduced logic swing without requiring restoration circuitry. Using a 0.35μm CMOS technology and a nominal supply voltage of 3.3V, a SCL full-adder 8 carry ripple adder (CRA) is implemented. It offers an or...

XOR & AND gates are most important basic building blocks of any VLSI applications. These gates can be implemented in different architectures by using different circuit designs techniques. This paper evaluates and compares the performance of various design techniques of XOR-AND gates. The performances of these techniques have been evaluated by Tanner Tools V13 using the 90nm CMOS technology. In ...

Designing reliable CMOS chips involve careful circuit design with attention directed to some of the potential reliability problems such as electromigration and hot carrie:r effects. This paper considers logic synthesis to handle electromigration and hot carrier degradation early in the design. phase. The electromigration and the hot carier effects are est,imated at the gate level using signal a...

Modern CMOS based advanced digital circuits suffer unwanted switching transients referred as ‘hazard’, due to ununilateral propagation delays. The hazard in combinational circuit results from a single variable change when the output should not have been altered or manipulated. The hazardous behavior of the logic circuit often creates a glitch. The glitching effect is negligible in very small ci...

In this paper a new approach is introduced for implementing the basic logic functions using analog current-mode techniques. By expanding the logic functions in power series expressions, and using summers and multipliers, realization of the basic logic functions is simplified. To illustrate the proposed technique, a CMOS circuit for simultaneous realization of the logic functions NOT, OR, NAND a...

Spin wave devices can be used to build generic logic functions. Their low-power property offers competitive potential in future applications. In this project, ideas of implementing Spin Wave Logic are discussed. It is seen that low-power logic structure is possible and CMOS interface circuit is available if the size of single Spin Wave Logic block is limited by practical concerns (e. g. routing...

This paper proposes a GateRL that is an automated circuit design framework of CMOS logic gates based on reinforcement learning. Because there are constraints in the connection elements, action masking scheme employed. It also reduces size space leading to improvement learning speed. The consists agent for and environment state, mask, reward. State reward generated from matrix describes current ...