In this paper we consider practical approach for identification of types of functional faults caused by shorts in conductive layers of IC layout and estimation of probability of occurrence of identified faults.

Every linguist dreams of the day when the intricate variety of human language will be a commonplace, widely understood in our own and other cultures; when we can unlock the secrets of human thought and communication; when people will stop asking us how many languages we speak. This day has not yet arrived; but the present book brings it somewhat closer. It is, to begin with, a very attractive b...

Satellite layout is a very hard task because available space for the instruments is small and the physical constraints on the layout are strong. In this article, we show how some physical layout constraints can be modeled geometrically and how Minkowski operations can be used to place instruments, and in particular antennas. The crucial step consists in placing an antenna by translation onto a ...

On-Chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and grou...

We present in this paper an overview of circuit techniques dedicated to design reliable low-voltage (1-V and below) analog functions in deep submicron standard CMOS processes. The challenges of designing such low-voltage and reliable analog building blocks are addressed both at circuit and physical layout levels. State-ofthe-art circuit topologies and techniques (input level shifting, bulk and ...

A flux shuttle shift register with master and slave sections is implemented with YBCO Josephson junctions along only one straight grain boundary of a bicrystal substrate. The investigated prototype comprises a write circuit, four master/slave shift register cells and a dynamic read out circuit for single flux quanta. The simulation results and the layout are presented.

FPGA-based synthesis tools require information about behaviour and architectural to make effective use of the limited number of cells typically available. A hardware description language which models layout and behaviour is used to elegantly specify circuit architecture. This source level information is used to efficiently translate circuit descriptions onto FPGA devices.

A new algorithm has been designed and implemented, that allows for the automatic generation of an optimum 2D and 3D grid for device simulation from the information available at the circuit-layout level. The tool fills a gap in the top-down design chain of integrated circuits, easing the task of circuit designers who are often unaware of specific features of device-modeling tools.

101 The Design of an SRAM-Based Field-Programmable Gate Array, Part II: Circuit Design and Layout Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard P aez-Monz on and Immanuel Rahardja Abstract|Field-Programmable Gate Arrays (FPGAs) are now widely used for the implementation of digital systems and many commercial architectures are available. Although the literature and data books conta...