Long-term reliability of processors in embedded systems is experiencing growing attention since decreasing feature sizes and increasing power consumption have a negative influence on the lifespan. Among other measures, the reliability can be influenced significantly by Dynamic Power Management (DPM), since it affects the processor’s temperature. Compared to single-core systems reconfigurable mu...

At present, in the field of application of numerous IT, multi-core processors are widely used, the hardware development is much faster than the speed of software development. Multi-core processor software is using the design concept of single-core processor software, so this software is not highperformance and the performance processor is not fully played. This paper firstly introduces the trad...

A visit to the neighborhood PC retail store provides ample proof that we are in the multi-core era. The key differentiator among manufacturers today is the number of cores that they pack onto a single chip. The clock frequency of commodity processors has reached its limit, however, and is likely to stay below 4 GHz for years to come. As a result, adding cores is not synonymous with increasing c...

The paper presented an approach for extracting benefits of both unified cache and distributed cache approaches using Non Uniform cache architecture. ● The NUCA approach enables us to retain as many memory references on chip as possible, thus greatly reducing penalty due to off chip accesses ● The approach utilizes distance locality, thereby data is stored as close to the processor core as possi...

The Volta phase plate is a recently developed electron cryo-microscopy (cryo-EM) device that enables contrast enhancement of biological samples. Here we have evaluated the potential of combining phase-plate imaging and single particle analysis to determine the structure of a small protein-DNA complex. To test the method, we made use of a 200 kDa Nucleosome Core Particle (NCP) reconstituted with...

This paper describes a real-time hand gesture recognition system and its application to VCR remote control. Cascaded classifiers are used to detect a number of different hand poses. In order to detect a hand in real time, the detection algorithm is optimized for multi-core processors by distributing the operations to multiple cores and minimizing the data transmission between them. We have impl...

This paper presents an error rate-optimal approach to reducing processor power whereby a processor is designed from the ground up to deliberately allow voltage overscaling-based timing errors during nominal operation, while a software or hardwarebased error resilience technique is used to tolerate these errors. This approach represents a shift from the traditional design philosophy of designing...

As integration densities continue to increase, interconnection has become one of the most important factors in determining the performance of multi-core processors. Recently, in order to reduce the delay due to interconnection, many studies have focused on the 3D multi-core processors. Compared to 2D multi-core architecture, 3D multi-core architecture gets decreased interconnection delay and lo...

The emergence of multi-core architectures has lead to the challenge of its efficient utilization. A comprehensive understanding of performance issues for these architectures is required to materialize any performance gains. This research conducts measurement based performance benchmarking and evaluation for multi-core processors based systems. It comprises of four phases: (1) design of an accur...

Background A systematic review of core outcome sets (COS) identified 250 reports relating to 198 studies [1]. The review showed that a range of methods have been used, in a variety of ways, to develop core outcome sets. Furthermore, we found that of the 178 studies that described the methods they used to determine the core outcome set, 164 (92%) did not provide an explanation regarding their ch...