This paper presents a circuit implementation and new architecture of one dimensional median filter. Normally, digital adder affects the overall circuit performance. The proposed method low area carry select adder (CSLA) is mostly used in digital circuits and high speed applications. Due to the presence of two Ripple Carry adders (RCA) in the structure, regular square root CSLA absorbs more powe...

This paper proposes a design of low power and low delay digital finite-impulse response (FIR) filter. Nowadays, there are many portable applications requiring low power and high throughput than ever before. Thus, low power system design has become a significant performance goal. The Finite Impulse Response (FIR) Filter is the important component for designing an efficient digital signal process...

RISC architecture is used across a wide range of platforms from Cellular phones to super computers.In this paper,a 16bit RISC processor is designed, which utilizes minimum functional units without compromising in performance. The design is based on architectural modification made in the incrementer circuit which is used in program counter.A Low Power Area Efficient carry select adder and a high...

Received Jan 15, 2015 Revised Jun 9, 2015 Accepted Jul 12, 2015 Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI (Gate Diffusion Input) Technique. Modified G...

Carry Select Adder (CSLA) is one of the high speed adders used in many computational systems to perform fast arithmetic operations. From the structure of the CSLA, it is clear that there is scope for reducing the gate count and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the logic resources and power of the CSLA. Based on ...

To reduce power utilization and area are some of the most important criteria for the fabrication of Digital Signal Processing and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. In most of the multiplication, the multiplier is an energyhungry component. To improve energy efficiency of multipliers, the choice of multiplier is very important. Her...

This paper presents a low power logic family, called asynchronous fine-grain power-gated logic (AFPL). Each pipeline stage is comprised of the logic function called efficient charge recovery logic (ECRL) gatesand a handshake controller. ECRL gates have negligible leakage power dissipation. By incorporatingpartial charge reuse (PCR) mechanism the energy dissipation required to complete the evalu...

In this paper focuses on carry -look ahead adders have done research on the design of high-speed, low-area, or low-power adders. Addition is the fundamental operation for any VLSI processors or digital signal processing. The main objective of this paper is to reduce the propagation delay and gate count of the Carry look-Ahead Adder (CLA).Which will also reflect in the reduction of area and powe...

Flexibility and Portability has increased the requirement of Low Power components in fields like multimedia, signal processing and other computing applications. Adders are the essential computing elements in such applications. However the present adder architectures with hybrid/heterogeneous features provide performance variations but limits to consume less power. In this paper, low power heter...