In the design of Integrated circuits, area plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in many dataprocessing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 4 bit, 8 bit, 16 bit, ...

A design of high performance 64 bit Multiplier-andAccumulator (MAC) is implemented in this paper. MAC unit performs important operation in many of the digital signal processing (DSP) applications. The multiplier is designed using modified Wallace multiplier and the adder is done with carry save adder. The total design is coded with Synthesize and simulate by verilog-HDL.

Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial multipliers obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of digit-serial multipliers is present...

This paper presents a bit-serial architecture for efficient addition and multiplication in binary finite fields GF(2m) using a polynomial basis representation. Moreover, a low-voltage/low-power implementation of the arithmetic circuits and the registers is proposed. The introduced multiplier operates over a variety of binary fields up to an order of 2m. We detail that the bit-serial multiplier ...

This paper presents the design redundant Binary multiplier for 32*32bit number multiplication. Modern computer system is a dedicated and very high speed unique multiplier. Therefore, this paper presents the design a Redundant Binary multiplier. The proposed system generates M, N and interconnected blocks. By extending bit of the operands and generating an additional product the proposed system ...

A NULL Cycle Reduction (NCR) technique is developed to increase the throughput of NULL Convention Logic systems, by reducing the time required to flush complete DATA wavefronts, commonly referred to as the NULL cycle. The NCR technique exploits parallelism by partitioning input wavefronts, such that one circuit processes a DATA wavefront, while its duplicate processes a NULL wavefront. A NCR ar...

This paper presents high speed digital Finite Impulse Response (FIR) filter relying on Wallace tree multiplier and Carry Select Adder (CSLA). Adder has three architectures such as basic CSLA using RCA (Ripple Carry Adder), CSLA using BEC (Binary to Excess-1 Converter) and CSLA using D-latch. In this paper we propose 4tap FIR Filter architecture using 16-bit CSLA using D-latch and 8-bit Wallace ...

This paper presents a throughput/area-efficient hardware accelerator architecture for elliptic curve point multiplication (ECPM) computation over GF(2233). The throughput of the proposed design is optimized by reducing total clock cycles using bit-parallel Karatsuba modular multiplier. We employ two techniques to minimize resources: (i) consolidated arithmetic unit where we combine single adder...

Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing technology is an advanced transmission technique for wireless communication systems. In this paper, the 64 point pipeline FFT/IFFT processor is introduced for efficient implementation of OFDM architecture. The IFFT processor is used to modulate the subcarrier in transmitter section and FFT processor demodulate the subcarr...

Montgomery multiplication in GF(2m) is defined by a(x)b(x)r 1(x) mod f(x), where the field is generated by irreducible polynomial f(x), a(x) and b(x) are two field elements in GF(2m), and r(x) is a fixed field element in GF(2m). In this paper, first we present a generalized Montgomery multiplication algorithm in GF(2m). Then by choosing r(X) according to f(x), we show that efficient architectur...