Digital design is an amazing and very broad field. The applications of digital design are present in our daily life, including Computers, calculators, video cameras etc. In fact, there will be always need for high speed and low power digital products which makes digital design a future growing business. Low power and high speed is challenging work in processor design. Implementing power optimiz...

Owning a high-end semiconductor foundry is luxury very few companies can afford. Thus, fabless design outsource integrated circuit fabrication to third parties. Within foundries, rogue elements may gain access the customer’s layout and perform malicious acts, including insertion of hardware trojan (HT). Many works focus on structure/effects HT, while have demonstrated viability their HTs in sil...

The design of a Duty-Cycled PLL (DCPLL) capable of burst mode operation is presented. The proposed DCPLL is a moderately-accurate low-power high-frequency synthesizer suitable for use in nodes for Wireless Sensor Networks (WSN) applications. Thanks to a dual loop configuration the PLL’s total frequency error, once in lock, is less than 0.25% from 300 MHz to 1.2 GHz. It employs a fast start-up D...

This paper presents a fully implantable, wirelessly powered subcutaneous amperometric biosensor. We propose a novel ultra-low power all-digital phase-locked loop (ADPLL) based potentiostat architecture for electrochemical sensing. The system is wirelessly powered by near-field RF coupling of an on-chip antenna to an external coil at 915 MHz. Bi-directional wireless telemetry supports data trans...

Improving interference robustness in Ultra-Low Power (ULP) receivers is a big challenge due to their low power budget. This paper presents an envelope detector based 915MHz 10kbps ULP receiver, which is fabricated in 65nm CMOS process for Wireless Sensor Networks (WSN) and Internet of Things (IoT). Two power-efficient techniques: Transmitted-Reference and Shifted Limiter, are proposed to improv...

AbstractAn EMI Camera LSI (EMcam) with a 12 x 4 on-chip 250μm x 50μm loop antenna matrix in 65nm CMOS is developed. EMcam achieves both the 2D electric scanning and 60μm-level spatial precision for the first time. The down-conversion architecture increases the bandwidth of EMcam and enables the measurement of EMI spectrum. Shared IF block scheme is proposed to alleviate the increasing power and...

Synchronizers play a key role in multi-clock domain systems on chip. Designing reliable synchronizers requires estimating and evaluating synchronizer parameters (resolution time constant) and (metastability window). Typically, evaluation of these parameters has been done by empirical rules of thumb or simple circuit simulations to ensure that the synchronizer MTBF is sufficiently long. This pap...

This paper presents a fully integrated all-digital ultra-wideband (UWB) transmitter. All functional blocks in the transmitter are implemented with digital standard cells and automatically placed-and-routed (APR-ed) by design tools. The center frequency and the bandwidth of the UWB pulses are digitally tuned to compensate for variations, and a calibration scheme utilizing APR mismatch is explore...

This paper presents a 12b 180 MS/s partial-interleaving Pipelined-SAR analog-to-digital converter (ADC). The 1st-stage is implemented with a 2b/cycle SAR ADC for high speed, where we propose a merged-residue-DAC technique to improve the noise performance. The capacitor pre-charging in conventional 2b/cycle operation wastes settling time and switching energy, while with this design approach the ...